Module Hardcaml.Always

Always is a DSL that lets one describe a circuit in the same style as a Verliog always block.

if and switch control constructs are provided. (<--) is used for assignment.

Code is written as lists of assignments, if and control statements.

variables;

let var = wire (zero 8) in
let var = reg r_sync enable 8 in

assignment;

var <-- exp;

if statements;

if_ condition [ ... ] [ ... ]

switch statements;

switch condition [
  of_int ~width:3 0, [ ... ];
  of_int ~width:3 1, [ ... ];
  of_int ~width:3 2, [ ... ];
  of_int ~width:3 3, [ ... ];
]

signals;

let (s:signal) = q (v:guarded) in

compilation;

compile [ ... ]

example;

      let state = reg r_sync enable 2 in
      let a = wire 8 in
      compile [
        if_ (a.value ==:. 4) [
          a <-- of_int ~width:8 2
        ] [
          switch state.value [
          (of_int ~width:2 0) [
            a <--. 3;
            state <-- of_int ~width:2 1;
          ];
          (of_int ~width:2 1) [
            a <--. 2;
            state <-- of_int ~width:2 2;
          ];
          (of_int ~width:2 2) [
            a <--. 1;
            state <-- of_int ~width:2 3;
          ];
          (of_int ~width:2 3) [
            a <--. 0;
            state <-- of_int ~width:2 4;
          ]
        ]
      ];
      let state = state.value in
      let a = a.value in
      ....