Module Always.Variable
The type of variables in guarded assignments. Variables may be asychronous wires, or synchronous regs. The current value of the variable may be accessed through the value field below.
val reg : Reg_spec.t -> enable:Signal.t -> width:Hardcaml__.Import.int -> tcreate a register
val pipeline : depth:Hardcaml__.Import.int -> Reg_spec.t -> enable:Signal.t -> width:Hardcaml__.Import.int -> tcreate a pipeline of registers