Module Ram.Write_port
type t= Signal.write_port={write_clock : Signal.t;write_address : Signal.t;write_enable : Signal.t;write_data : Signal.t;}
val sexp_of_t : t -> Ppx_sexp_conv_lib.Sexp.t
Ram.Write_porttype t = Signal.write_port = {write_clock : Signal.t; |
write_address : Signal.t; |
write_enable : Signal.t; |
write_data : Signal.t; |
}val sexp_of_t : t -> Ppx_sexp_conv_lib.Sexp.t