Module `Hardcaml.Ram`

Random access memories described using RTL inference.

Can be specified with arbitrary numbers of read and write ports, though in reality only up to 1 of each can be inferred by a synthesizer.

module Collision_mode : sig ... end

module Write_port : sig ... end

module Read_port : sig ... end

val create : collision_mode:Collision_mode.t -> size:Hardcaml__.Import.int -> write_ports:Write_port.t Hardcaml__.Import.array -> read_ports:Read_port.t Hardcaml__.Import.array -> Signal.t Hardcaml__.Import.array