Module Structural.Base1

include Hardcaml__.Comb_intf.Gates
type t
val sexp_of_t : t -> Ppx_sexp_conv_lib.Sexp.t
include Hardcaml__.Import.Equal.S with type t := t
type t
val equal : t Hardcaml__.Import.Equal.equal
val empty : t

the empty signal

val is_empty : t -> Hardcaml__.Import.bool
val width : t -> Hardcaml__.Import.int

returns the width of a signal

val of_constant : Hardcaml.Constant.t -> t

creates a constant

val to_constant : t -> Hardcaml.Constant.t
val concat : t Hardcaml__.Import.list -> t

concatenates a list of signals

val select : t -> Hardcaml__.Import.int -> Hardcaml__.Import.int -> t

select a range of bits

val (--) : t -> Hardcaml__.Import.string -> t

names a signal

val (&:) : t -> t -> t

bitwise and

val (|:) : t -> t -> t

bitwise or

val (^:) : t -> t -> t

bitwise xor

val (~:) : t -> t

bitwise not

val to_string : t -> Hardcaml__.Import.string

create string from signal

val mux : t -> t Hardcaml__.Import.list -> t

multiplexer

val (+:) : t -> t -> t

addition

val (-:) : t -> t -> t

subtraction

val (*:) : t -> t -> t

unsigned multiplication

val (*+) : t -> t -> t

signed multiplication

val (==:) : t -> t -> t

equality

val (<:) : t -> t -> t

less than