Module Ram.Write_port

type t = Hardcaml.Signal.write_port = {
write_clock : Hardcaml.Signal.t;
write_address : Hardcaml.Signal.t;
write_enable : Hardcaml.Signal.t;
write_data : Hardcaml.Signal.t;
}
val sexp_of_t : t -> Ppx_sexp_conv_lib.Sexp.t