Parameter Make.1-B
val sexp_of_t : t -> Ppx_sexp_conv_lib.Sexp.t
val empty : tthe empty signal
val is_empty : t -> Hardcaml__.Import.boolval (--) : t -> Hardcaml__.Import.string -> tnames a signal
let a = a -- "a" in ...signals may have multiple names.
val width : t -> Hardcaml__.Import.intreturns the width (number of bits) of a signal.
let w = width s in ...
val address_bits_for : Hardcaml__.Import.int -> Hardcaml__.Import.intaddess_bits_for num_elementsreturns the address width required to indexnum_elements.It is the same as
Int.ceil_log2, except it wll return a minimum value of 1 (since you cannot have 0 width vectors). Raises ifnum_elementsis< 0.
val num_bits_to_represent : Hardcaml__.Import.int -> Hardcaml__.Import.intnum_bits_to_represent xreturns the number of bits required to represent the numberx, which should be>= 0.
val of_constant : Hardcaml.Constant.t -> tval to_constant : t -> Hardcaml.Constant.tval constb : Hardcaml__.Import.string -> tconvert binary string to constant
val consti : width:Hardcaml__.Import.int -> Hardcaml__.Import.int -> tconvert integer to constant
val consti32 : width:Hardcaml__.Import.int -> Hardcaml__.Import.int32 -> tval consti64 : width:Hardcaml__.Import.int -> Hardcaml__.Import.int64 -> tval consthu : width:Hardcaml__.Import.int -> Hardcaml__.Import.string -> tconvert unsigned hex string to constant
val consths : width:Hardcaml__.Import.int -> Hardcaml__.Import.string -> tconvert signed hex string to constant
val constd : width:Hardcaml__.Import.int -> Hardcaml__.Import.string -> tconvert decimal string to constant
val constv : Hardcaml__.Import.string -> tconvert verilog style string to constant
val constibl : Hardcaml__.Import.int Hardcaml__.Import.list -> tconvert IntbitsList to constant
val const : Hardcaml__.Import.string -> tconvert verilog style or binary string to constant
val concat : t Hardcaml__.Import.list -> tconcat tsconcatenates a list of signals - the msb of the head of the list will become the msb of the result.let c = concat [ a; b; c ] in ...concatraises iftsis empty or if anytintsis empty.
val concat_e : t Hardcaml__.Import.list -> tsame as
concatexcept empty signals are first filtered out
val vdd : tlogic 1
val is_vdd : t -> Hardcaml__.Import.boolval gnd : tlogic 0
val is_gnd : t -> Hardcaml__.Import.boolval zero : Hardcaml__.Import.int -> tzero wmakes a the zero valued constant of widthw
val ones : Hardcaml__.Import.int -> tones wmakes a constant of all ones of widthw
val one : Hardcaml__.Import.int -> tone wmakes a one valued constant of widthw
val select : t -> Hardcaml__.Import.int -> Hardcaml__.Import.int -> tselect t hi loselects fromtbits in the rangehi...lo, inclusive.selectraises unlesshiandlofall within0 .. width t - 1andhi >= lo.
val select_e : t -> Hardcaml__.Import.int -> Hardcaml__.Import.int -> tsame as
selectexcept invalid indices returnempty
val bit : t -> Hardcaml__.Import.int -> tselect a single bit
val drop_bottom : t -> Hardcaml__.Import.int -> tdrop_bottom s ndrop bottomnbits ofs
val drop_top : t -> Hardcaml__.Import.int -> tdrop_top s ndrop topnbits ofs
val sel_bottom : t -> Hardcaml__.Import.int -> tsel_bottom s nselect bottomnbits ofs
val sel_top : t -> Hardcaml__.Import.int -> tsel_top s nselect topnbits ofs
val insert : into:t -> t -> at_offset:Hardcaml__.Import.int -> tinsert ~into:t x ~at_offsetinsertxintotat given offet
val sel : t -> (Hardcaml__.Import.int * Hardcaml__.Import.int) -> tval mux : t -> t Hardcaml__.Import.list -> tmultiplexer.
let m = mux sel inputs in ...Given
l=List.length inputsandw=width selthe following conditions must hold.l<= 2**w,l>= 2If
l< 2**w, the last input is repeated.All inputs provided must have the same width, which will in turn be equal to the width of
m.
val mux2 : t -> t -> t -> tmux2 c t f2 input multiplexer. Selectstifcis high otherwisef.tandfmust have same width andcmust be 1 bit.Equivalent to
mux c [f; t]
val mux_init : t -> Hardcaml__.Import.int -> f:(Hardcaml__.Import.int -> t) -> tval cases : t -> t -> (Hardcaml__.Import.int * t) Hardcaml__.Import.list -> tcase mux
val matches : ?resize:(t -> Hardcaml__.Import.int -> t) -> ?default:t -> t -> (Hardcaml__.Import.int * t) Hardcaml__.Import.list -> tmatch mux
val (^:.) : t -> Hardcaml__.Import.int -> tval (~:) : t -> tlogical not
val (-:.) : t -> Hardcaml__.Import.int -> tval negate : t -> tnegation
val (>=+.) : t -> Hardcaml__.Import.int -> tval to_string : t -> Hardcaml__.Import.stringcreate string from signal
val to_int : t -> Hardcaml__.Import.intto_int ttreatstas unsigned and resizes it to fit exactly within an OCamlInt.t.- If
width t > Int.num_bitsthen the upper bits are truncated. - If
width t >= Int.num_bitsandbit t (Int.num_bits-1) = vdd(i.e. the msb of the resultingInt.tis set), then the result is negative. - If
tisSignal.tand not a constant value, an exception is raised.
- If
val to_sint : t -> Hardcaml__.Import.intto_sint ttreatstas signed and resizes it to fit exactly within an OCamlInt.t.- If
width t > Int.num_bitsthen the upper bits are truncated. - If
tisSignal.tand not a constant value, an exception is raised.
- If
val to_int32 : t -> Hardcaml__.Import.int32val to_sint32 : t -> Hardcaml__.Import.int32val to_int64 : t -> Hardcaml__.Import.int64val to_sint64 : t -> Hardcaml__.Import.int64val to_bstr : t -> Hardcaml__.Import.stringcreate binary string from signal
val bits : t -> t Hardcaml__.Import.listconvert signal to a list of bits, msb first
val to_array : t -> t Hardcaml__.Import.arrayto_array sconvert signalsto array of bits with lsb at index 0
val of_array : t Hardcaml__.Import.array -> tof_array aconvert arrayaof bits to signal with lsb at index 0
val repeat : t -> Hardcaml__.Import.int -> trepeat signal n times
val split : ?exact:Hardcaml__.Import.bool -> part_width:Hardcaml__.Import.int -> t -> t Hardcaml__.Import.listSplit signal into a list of signals with width equal to
part_width. The least significant bits are at the head of the returned list. Ifexactistruethe input signal width must be exactly divisable bypart_width.
val sll : t -> Hardcaml__.Import.int -> tshift left logical
val srl : t -> Hardcaml__.Import.int -> tshift right logical
val sra : t -> Hardcaml__.Import.int -> tshift right arithmetic
val uresize : t -> Hardcaml__.Import.int -> turesize t wreturns the unsigned resize oftto widthw. Ifw = width t, this is a no-op. Ifw < width t, thisselects thewlow bits oft. Ifw > width t, this extendstwithzero (width t - w).
val sresize : t -> Hardcaml__.Import.int -> tsresize t wreturns the signed resize oftto widthw. Ifw = width t, this is a no-op. Ifw < width t, thisselects thewlow bits oft. Ifw > width t, this extendstwithwidth t - wcopies ofmsb t.
val resize_list : resize:(t -> Hardcaml__.Import.int -> t) -> t Hardcaml__.Import.list -> t Hardcaml__.Import.listresize_list ?resize lfinds the maximum width inland appliesresize el maxto each element.
val resize_op2 : resize:(t -> Hardcaml__.Import.int -> t) -> (t -> t -> t) -> t -> t -> tresize_op2 ~resize f a bappliesresize x wtoaandbwherewis the maximum of their widths. It then returnsf a b
val reduce : f:('a -> 'a -> 'a) -> 'a Hardcaml__.Import.list -> 'afold 'op' though list
val mod_counter : max:Hardcaml__.Import.int -> t -> tmod_counter max tisif t = max then 0 else (t + 1), and can be used to count from 0 to (max-1) then from zero again. If max == 1<<n, then a comparator is not generated and overflow arithmetic used instead. If
val tree : arity:Hardcaml__.Import.int -> f:('a Hardcaml__.Import.list -> 'a) -> 'a Hardcaml__.Import.list -> 'atree ~arity ~f inputcreates a tree of operations. The arity of the operator is configurable.treeraises ifinput = [].
val priority_select : (t Hardcaml.With_valid.t Hardcaml__.Import.list -> t Hardcaml.With_valid.t) Hardcaml__.Comb_intf.optional_branching_factorpriority_select casesreturns the value associated with the first case whosevalidsignal is high.validwill be set low in the returnedWith_valid.tif no case is selected.
val priority_select_with_default : (t Hardcaml.With_valid.t Hardcaml__.Import.list -> default:t -> t) Hardcaml__.Comb_intf.optional_branching_factorSame as
priority_selectexcept returnsdefaultif no case matches.
val onehot_select : (t Hardcaml.With_valid.t Hardcaml__.Import.list -> t) Hardcaml__.Comb_intf.optional_branching_factorSelect a case where one and only one
validsignal is enabled. If more than one case isvalidthen the return value is undefined. If no cases are valid,0is returned by the current implementation, though this should not be relied upon.
val popcount : (t -> t) Hardcaml__.Comb_intf.optional_branching_factorpopcount treturns the number of bits set int.
val is_pow2 : (t -> t) Hardcaml__.Comb_intf.optional_branching_factoris_pow2 treturns a bit to indicate iftis a power of 2.
val leading_ones : (t -> t) Hardcaml__.Comb_intf.optional_branching_factorleading_ones treturns the number of consecutive1s from the most significant bit oftdown.
val trailing_ones : (t -> t) Hardcaml__.Comb_intf.optional_branching_factortrailing_ones treturns the number of consecutive1s from the least significant bit oftup.
val leading_zeros : (t -> t) Hardcaml__.Comb_intf.optional_branching_factorleading_zeros treturns the number of consecutive0s from the most significant bit oftdown.
val trailing_zeros : (t -> t) Hardcaml__.Comb_intf.optional_branching_factortrailing_zeros treturns the number of consecutive0s from the least significant bit oftup.
val floor_log2 : (t -> t Hardcaml.With_valid.t) Hardcaml__.Comb_intf.optional_branching_factorfloor_log2 xreturns the floor of log-base-2 ofx.xis treated as unsigned and an error is indicated byvalid = gndin the return value ifx = 0.
val ceil_log2 : (t -> t Hardcaml.With_valid.t) Hardcaml__.Comb_intf.optional_branching_factorceil_log2 xreturns the ceiling of log-base-2 ofx.xis treated as unsigned and an error is indicated byvalid = gndin the return value ifx = 0.
val random : width:Hardcaml__.Import.int -> tcreate random constant vector of given width
module type TypedMath : Hardcaml__.Comb_intf.TypedMath with type t := t