Module Hardcaml.Scope

module Path : sig ... end
module Naming_scheme : sig ... end

Control of name generation in a hierarchy of modules. The position of a module within a hierarchy is determined by a path which leads back to the (single) top most parent module. Signal names may be pre-pended with some represtation of that path.

type t
val sexp_of_t : t -> Ppx_sexp_conv_lib.Sexp.t
val create : ?⁠flatten_design:Hardcaml__.Import.bool -> ?⁠naming_scheme:Naming_scheme.t -> ?⁠name:Hardcaml__.Import.string -> Hardcaml__.Import.unit -> t

create ?flatten_design ?naming_scheme ?name () creates a new scope. If flatten_design is true, then all module instantions are inlined. Names for wires are determiend by naming_scheme.

val sub_scope : t -> Hardcaml__.Import.string -> t

sub_scope t label returns a new scope with label appended to its hierarchical path

val path : t -> Path.t

path t returns the Path.t associated with t. This will determine the prefix used when naming modules that are associated with this scope.

val circuit_database : t -> Circuit_database.t

circuit_database t returns the circuit database associated with t. Note that circuit databases are shared among sub_scopes.

val flatten_design : t -> Hardcaml__.Import.bool

flatten_design t returns true when HardCaml will inline all module instantiations.

val naming_scheme : t -> Naming_scheme.t

naming_scheme t returns the Naming.t that t was constructed with.

val naming : ?⁠sep:Hardcaml__.Import.string -> t -> Signal.t -> Hardcaml__.Import.string -> Signal.t

naming ?sep t signal name assigns a heirarchical name to signal based on the path of t and name. sep, when provided, determines the separator for path components in the heirarchical name.

This is typically used as a partial application to construct a new signal naming operator, .e.g:

let (--) = naming scope in
(* ... other code ... *)
let named_signal = some_signal -- "data" in
(* ... more code ... *)