Module Hardcaml.Reg_spec

include Signal.Reg_spec_
type t = Signal.register
val sexp_of_t : t -> Ppx_sexp_conv_lib.Sexp.t
val create : ?⁠clear:Signal.signal -> ?⁠reset:Signal.signal -> Hardcaml__.Import.unit -> clock:Signal.signal -> t
val override : ?⁠clock:Signal.signal -> ?⁠clock_edge:Edge.t -> ?⁠reset:Signal.signal -> ?⁠reset_edge:Edge.t -> ?⁠reset_to:Signal.signal -> ?⁠clear:Signal.signal -> ?⁠clear_level:Level.t -> ?⁠clear_to:Signal.signal -> ?⁠global_enable:Signal.signal -> t -> t
val clock : t -> Signal.signal
val clear : t -> Signal.signal
val reset : t -> Signal.signal