Module Hardcaml.Fifo

Synchronous FIFO.

type t = {
q : Signal.t;
full : Signal.t;
empty : Signal.t;
nearly_full : Signal.t;
nearly_empty : Signal.t;
used : Signal.t;
}
val sexp_of_t : t -> Ppx_sexp_conv_lib.Sexp.t
val create : ?⁠nearly_empty:Hardcaml__.Import.int -> ?⁠nearly_full:Hardcaml__.Import.int -> ?⁠overflow_check:Hardcaml__.Import.bool -> ?⁠reset:Signal.t -> ?⁠showahead:Hardcaml__.Import.bool -> ?⁠underflow_check:Hardcaml__.Import.bool -> Hardcaml__.Import.unit -> capacity:Hardcaml__.Import.int -> clock:Signal.t -> clear:Signal.t -> wr:Signal.t -> d:Signal.t -> rd:Signal.t -> t

create ~clk ~clr ~wr ~d ~rd capacity builds a FIFO with capacity elements which is written with d when wr is high and read when rd is high.

The default reset configuration is to use a synchronous clr signal. An asynchronous rst may be optionally provided. One of clr or rst must be non-empty.

Optional overflow and underflow checking may be used. Data will not be written(/read) when the fifo is full(/empty) regardles or the wr/(rd) signals.

nearly_emtpy and nearly_full may be programmed to go high when the fifo is nearing an underflow or overflow state.

The showahead mode changes the read behaviour of the FIFO. When showahead is false read data is available 1 cycle after rd is high. With showahead true the data is available on the same cycle as rd is high. To support showahead behaviour the timing of the full/empty flag also changes (although they still correctly indicate when it is safe to read or write to the FIFO). showahead mode has some extra cost in terms of extra logic and reduced frequency.

Note; showahead is sometimes referred to as "first word fall through".

The used output indicates the number of elements currently in the FIFO.