Module Hardcaml.Cosim

Icarus Verilog Cosimulation interface

type delta_message = {
sets : (Hardcaml__.Import.string * Hardcaml__.Import.string) Hardcaml__.Import.list;
gets : Hardcaml__.Import.string Hardcaml__.Import.list;
delta_time : Hardcaml__.Import.int64;
}

run sets, then gets then schedule next callback at cur_time+delta_time

type init_message = Hardcaml__.Import.string Hardcaml__.Import.list

expected inputs and outputs

type control_message =
| Finish
| Run of delta_message

control message

type response_message = (Hardcaml__.Import.string * Hardcaml__.Import.string) Hardcaml__.Import.list

response message

val net_addr : Hardcaml__.Import.string
val net_port : Hardcaml__.Import.int
module Comms : sig ... end

basic TCP communications between client (simulation) and server (hardcaml)

val control : Unix.file_descr -> control_message -> response_message

send a control message to the simulation

val write_testbench : ?⁠dump_file:Hardcaml__.Import.string -> name:Hardcaml__.Import.string -> inputs:(Hardcaml__.Import.string * Hardcaml__.Import.int) Hardcaml__.Import.list -> outputs:(Hardcaml__.Import.string * Hardcaml__.Import.int) Hardcaml__.Import.list -> (Hardcaml__.Import.string -> Hardcaml__.Import.unit) -> Hardcaml__.Import.unit

write test harness

val write_testbench_from_circuit : ?⁠dump_file:Hardcaml__.Import.string -> (Hardcaml__.Import.string -> Hardcaml__.Import.unit) -> Circuit.t -> Hardcaml__.Import.unit

write test hardness derivied from a hardcaml circuit

val compile : Hardcaml__.Import.string Hardcaml__.Import.list -> Hardcaml__.Import.string -> Hardcaml__.Import.unit

compile verilog files to a vvp simulation object

val derive_clocks_and_resets : Circuit.t -> Hardcaml__.Import.string Hardcaml__.Import.list * Hardcaml__.Import.string Hardcaml__.Import.list

find clocks and resets in a hardcaml circuit

val load_sim : Hardcaml__.Import.string -> Hardcaml__.Import.unit

load vvp file into simulator along with vpi object

val compile_and_load_sim : ?⁠dump_file:Hardcaml__.Import.string -> Circuit.t -> Hardcaml__.Import.unit

compile circuit and load simulation

val init_sim : (Hardcaml__.Import.unit -> Hardcaml__.Import.unit) -> (Hardcaml__.Import.string * Hardcaml__.Import.int) Hardcaml__.Import.list -> (Hardcaml__.Import.string * Hardcaml__.Import.int) Hardcaml__.Import.list -> Unix.file_descr
val make_sim_obj : server:Unix.file_descr -> clocks:(Hardcaml__.Import.string * Hardcaml__.Import.int) Hardcaml__.Import.list -> resets:(Hardcaml__.Import.string * Hardcaml__.Import.int) Hardcaml__.Import.list -> inputs:(Hardcaml__.Import.string * Hardcaml__.Import.int) Hardcaml__.Import.list -> outputs:(Hardcaml__.Import.string * Hardcaml__.Import.int) Hardcaml__.Import.list -> Cyclesim.t_port_list
val make : ?⁠dump_file:Hardcaml__.Import.string -> Circuit.t -> Cyclesim.t_port_list

create simulator from hardcaml circuit

val load : clocks:(Hardcaml__.Import.string * Hardcaml__.Import.int) Hardcaml__.Import.list -> resets:(Hardcaml__.Import.string * Hardcaml__.Import.int) Hardcaml__.Import.list -> inputs:(Hardcaml__.Import.string * Hardcaml__.Import.int) Hardcaml__.Import.list -> outputs:(Hardcaml__.Import.string * Hardcaml__.Import.int) Hardcaml__.Import.list -> Hardcaml__.Import.string -> Cyclesim.t_port_list

load icarus vvp simulation

module With_interface : functor (I : Interface.S) -> functor (O : Interface.S) -> sig ... end