Module Comb.Make

Parameters

• Primitives : Primitives

Signature

type t = Primitives.t

val empty : t

the empty signal

val is_empty : t -> Hardcaml__.Import.bool

val (--) : t -> Hardcaml__.Import.string -> t

names a signal

let a = a -- "a" in ...

signals may have multiple names.

val width : t -> Hardcaml__.Import.int

returns the width (number of bits) of a signal.

let w = width s in ...

val address_bits_for : Hardcaml__.Import.int -> Hardcaml__.Import.int

addess_bits_for num_elements returns the address width required to index num_elements.

It is the same as Int.ceil_log2, except it wll return a minimum value of 1 (since you cannot have 0 width vectors). Raises if num_elements is < 0.

val num_bits_to_represent : Hardcaml__.Import.int -> Hardcaml__.Import.int

num_bits_to_represent x returns the number of bits required to represent the number x, which should be >= 0.

val of_constant : Constant.t -> t

val to_constant : t -> Constant.t

val constb : Hardcaml__.Import.string -> t

convert binary string to constant

val consti : width:Hardcaml__.Import.int -> Hardcaml__.Import.int -> t

convert integer to constant

val consti32 : width:Hardcaml__.Import.int -> Hardcaml__.Import.int32 -> t

val consti64 : width:Hardcaml__.Import.int -> Hardcaml__.Import.int64 -> t

val consthu : width:Hardcaml__.Import.int -> Hardcaml__.Import.string -> t

convert unsigned hex string to constant

val consths : width:Hardcaml__.Import.int -> Hardcaml__.Import.string -> t

convert signed hex string to constant

val constd : width:Hardcaml__.Import.int -> Hardcaml__.Import.string -> t

convert decimal string to constant

val constv : Hardcaml__.Import.string -> t

convert verilog style string to constant

val constibl : Hardcaml__.Import.int Hardcaml__.Import.list -> t

convert IntbitsList to constant

val const : Hardcaml__.Import.string -> t

convert verilog style or binary string to constant

val concat : t Hardcaml__.Import.list -> t

concat ts concatenates a list of signals - the msb of the head of the list will become the msb of the result.

let c = concat [ a; b; c ] in ...

concat raises if ts is empty or if any t in ts is empty.

val concat_e : t Hardcaml__.Import.list -> t

same as concat except empty signals are first filtered out

val (@:) : t -> t -> t

concatenate two signals.

let c = a @: b in ...

equivalent to concat [ a; b ]

val vdd : t

logic 1

val is_vdd : t -> Hardcaml__.Import.bool

val gnd : t

logic 0

val is_gnd : t -> Hardcaml__.Import.bool

val zero : Hardcaml__.Import.int -> t

zero w makes a the zero valued constant of width w

val ones : Hardcaml__.Import.int -> t

ones w makes a constant of all ones of width w

val one : Hardcaml__.Import.int -> t

one w makes a one valued constant of width w

val select : t -> Hardcaml__.Import.int -> Hardcaml__.Import.int -> t

select t hi lo selects from t bits in the range hi...lo, inclusive. select raises unless hi and lo fall within 0 .. width t - 1 and hi >= lo.

val select_e : t -> Hardcaml__.Import.int -> Hardcaml__.Import.int -> t

same as select except invalid indices return empty

val bit : t -> Hardcaml__.Import.int -> t

select a single bit

val msb : t -> t

get most significant bit

val lsbs : t -> t

get least significant bits

val lsb : t -> t

get least significant bit

val msbs : t -> t

get most significant bits

val drop_bottom : t -> Hardcaml__.Import.int -> t

drop_bottom s n drop bottom n bits of s

val drop_top : t -> Hardcaml__.Import.int -> t

drop_top s n drop top n bits of s

val sel_bottom : t -> Hardcaml__.Import.int -> t

sel_bottom s n select bottom n bits of s

val sel_top : t -> Hardcaml__.Import.int -> t

sel_top s n select top n bits of s

val insert : into:t -> t -> at_offset:Hardcaml__.Import.int -> t

insert ~into:t x ~at_offset insert x into t at given offet

val sel : t -> (Hardcaml__.Import.int * Hardcaml__.Import.int) -> t

val mux : t -> t Hardcaml__.Import.list -> t

multiplexer.

let m = mux sel inputs in ...

Given l = List.length inputs and w = width sel the following conditions must hold.

l <= 2**w, l >= 2

If l < 2**w, the last input is repeated.

All inputs provided must have the same width, which will in turn be equal to the width of m.

val mux2 : t -> t -> t -> t

mux2 c t f 2 input multiplexer. Selects t if c is high otherwise f.

t and f must have same width and c must be 1 bit.

Equivalent to mux c [f; t]

val mux_init : t -> Hardcaml__.Import.int -> f:(Hardcaml__.Import.int -> t) -> t

val cases : t -> t -> (Hardcaml__.Import.int * t) Hardcaml__.Import.list -> t

case mux

val matches : ?⁠resize:(t -> Hardcaml__.Import.int -> t) -> ?⁠default:t -> t -> (Hardcaml__.Import.int * t) Hardcaml__.Import.list -> t

match mux

val (&:) : t -> t -> t

logical and

val (&:.) : t -> Hardcaml__.Import.int -> t

val (&&:) : t -> t -> t

a <>:. 0 &: b <>:. 0

val (|:) : t -> t -> t

logical or

val (|:.) : t -> Hardcaml__.Import.int -> t

val (||:) : t -> t -> t

a <>:. 0 |: b <>:. 0

val (^:) : t -> t -> t

logic xor

val (^:.) : t -> Hardcaml__.Import.int -> t

val (~:) : t -> t

logical not

val (+:) : t -> t -> t

addition

val (+:.) : t -> Hardcaml__.Import.int -> t

val (-:) : t -> t -> t

subtraction

val (-:.) : t -> Hardcaml__.Import.int -> t

val negate : t -> t

negation

val (*:) : t -> t -> t

unsigned multiplication

val (*+) : t -> t -> t

signed multiplication

val (==:) : t -> t -> t

equality

val (==:.) : t -> Hardcaml__.Import.int -> t

val (<>:) : t -> t -> t

inequality

val (<>:.) : t -> Hardcaml__.Import.int -> t

val (<:) : t -> t -> t

less than

val (<:.) : t -> Hardcaml__.Import.int -> t

val lt : t -> t -> t

val (>:) : t -> t -> t

greater than

val (>:.) : t -> Hardcaml__.Import.int -> t

val (<=:) : t -> t -> t

less than or equal to

val (<=:.) : t -> Hardcaml__.Import.int -> t

val (>=:) : t -> t -> t

greater than or equal to

val (>=:.) : t -> Hardcaml__.Import.int -> t

val (<+) : t -> t -> t

signed less than

val (<+.) : t -> Hardcaml__.Import.int -> t

val (>+) : t -> t -> t

signed greater than

val (>+.) : t -> Hardcaml__.Import.int -> t

val (<=+) : t -> t -> t

signed less than or equal to

val (<=+.) : t -> Hardcaml__.Import.int -> t

val (>=+) : t -> t -> t

signed greated than or equal to

val (>=+.) : t -> Hardcaml__.Import.int -> t

val to_string : t -> Hardcaml__.Import.string

create string from signal

val to_int : t -> Hardcaml__.Import.int

to_int t treats t as unsigned and resizes it to fit exactly within an OCaml Int.t.

• If width t > Int.num_bits then the upper bits are truncated.
• If width t >= Int.num_bits and bit t (Int.num_bits-1) = vdd (i.e. the msb of the resulting Int.t is set), then the result is negative.
• If t is Signal.t and not a constant value, an exception is raised.

val to_sint : t -> Hardcaml__.Import.int

to_sint t treats t as signed and resizes it to fit exactly within an OCaml Int.t.

• If width t > Int.num_bits then the upper bits are truncated.
• If t is Signal.t and not a constant value, an exception is raised.

val to_int32 : t -> Hardcaml__.Import.int32

val to_sint32 : t -> Hardcaml__.Import.int32

val to_int64 : t -> Hardcaml__.Import.int64

val to_sint64 : t -> Hardcaml__.Import.int64

val to_bstr : t -> Hardcaml__.Import.string

create binary string from signal

val bits : t -> t Hardcaml__.Import.list

convert signal to a list of bits, msb first

val to_array : t -> t Hardcaml__.Import.array

to_array s convert signal s to array of bits with lsb at index 0

val of_array : t Hardcaml__.Import.array -> t

of_array a convert array a of bits to signal with lsb at index 0

val repeat : t -> Hardcaml__.Import.int -> t

repeat signal n times

val split_in_half : t -> t * t

split signal in half

val split : ?⁠exact:Hardcaml__.Import.bool -> part_width:Hardcaml__.Import.int -> t -> t Hardcaml__.Import.list

Split signal into a list of signals with width equal to part_width. The least significant bits are at the head of the returned list. If exact is true the input signal width must be exactly divisable by part_width.

val sll : t -> Hardcaml__.Import.int -> t

shift left logical

val srl : t -> Hardcaml__.Import.int -> t

shift right logical

val sra : t -> Hardcaml__.Import.int -> t

shift right arithmetic

val log_shift : (t -> Hardcaml__.Import.int -> t) -> t -> t -> t

shift by variable amount

val uresize : t -> Hardcaml__.Import.int -> t

uresize t w returns the unsigned resize of t to width w. If w = width t, this is a no-op. If w < width t, this selects the w low bits of t. If w > width t, this extends t with zero (width t - w).

val sresize : t -> Hardcaml__.Import.int -> t

sresize t w returns the signed resize of t to width w. If w = width t, this is a no-op. If w < width t, this selects the w low bits of t. If w > width t, this extends t with width t - w copies of msb t.

val ue : t -> t

unsigned resize by +1 bit

val se : t -> t

signed resize by +1 bit

val resize_list : resize:(t -> Hardcaml__.Import.int -> t) -> t Hardcaml__.Import.list -> t Hardcaml__.Import.list

resize_list ?resize l finds the maximum width in l and applies resize el max to each element.

val resize_op2 : resize:(t -> Hardcaml__.Import.int -> t) -> (t -> t -> t) -> t -> t -> t

resize_op2 ~resize f a b applies resize x w to a and b where w is the maximum of their widths. It then returns f a b

val reduce : f:('a -> 'a -> 'a) -> 'a Hardcaml__.Import.list -> 'a

fold 'op' though list

val reverse : t -> t

reverse bits

val mod_counter : max:Hardcaml__.Import.int -> t -> t

mod_counter max t is if t = max then 0 else (t + 1), and can be used to count from 0 to (max-1) then from zero again. If max == 1<<n, then a comparator is not generated and overflow arithmetic used instead. If

val tree : arity:Hardcaml__.Import.int -> f:('a Hardcaml__.Import.list -> 'a) -> 'a Hardcaml__.Import.list -> 'a

tree ~arity ~f input creates a tree of operations. The arity of the operator is configurable. tree raises if input = [].

val priority_select : (t With_valid.t Hardcaml__.Import.list -> t With_valid.t) Hardcaml__.Comb_intf.optional_branching_factor

priority_select cases returns the value associated with the first case whose valid signal is high. valid will be set low in the returned With_valid.t if no case is selected.

val priority_select_with_default : (t With_valid.t Hardcaml__.Import.list -> default:t -> t) Hardcaml__.Comb_intf.optional_branching_factor

Same as priority_select except returns default if no case matches.

val onehot_select : (t With_valid.t Hardcaml__.Import.list -> t) Hardcaml__.Comb_intf.optional_branching_factor

Select a case where one and only one valid signal is enabled. If more than one case is valid then the return value is undefined. If no cases are valid, 0 is returned by the current implementation, though this should not be relied upon.

val popcount : (t -> t) Hardcaml__.Comb_intf.optional_branching_factor

popcount t returns the number of bits set in t.

val is_pow2 : (t -> t) Hardcaml__.Comb_intf.optional_branching_factor

is_pow2 t returns a bit to indicate if t is a power of 2.

val leading_ones : (t -> t) Hardcaml__.Comb_intf.optional_branching_factor

leading_ones t returns the number of consecutive 1s from the most significant bit of t down.

val trailing_ones : (t -> t) Hardcaml__.Comb_intf.optional_branching_factor

trailing_ones t returns the number of consecutive 1s from the least significant bit of t up.

val leading_zeros : (t -> t) Hardcaml__.Comb_intf.optional_branching_factor

leading_zeros t returns the number of consecutive 0s from the most significant bit of t down.

val trailing_zeros : (t -> t) Hardcaml__.Comb_intf.optional_branching_factor

trailing_zeros t returns the number of consecutive 0s from the least significant bit of t up.

val floor_log2 : (t -> t With_valid.t) Hardcaml__.Comb_intf.optional_branching_factor

floor_log2 x returns the floor of log-base-2 of x. x is treated as unsigned and an error is indicated by valid = gnd in the return value if x = 0.

val ceil_log2 : (t -> t With_valid.t) Hardcaml__.Comb_intf.optional_branching_factor

ceil_log2 x returns the ceiling of log-base-2 of x. x is treated as unsigned and an error is indicated by valid = gnd in the return value if x = 0.

val binary_to_onehot : t -> t

convert binary to onehot

val onehot_to_binary : t -> t

convert onehot to binary

val binary_to_gray : t -> t

convert binary to gray code

val gray_to_binary : t -> t

convert gray code to binary

val random : width:Hardcaml__.Import.int -> t

create random constant vector of given width

module Uop : TypedMath with type v := t

Unsigned operations compatible with type t

module Sop : TypedMath with type v := t

Signed operations compatible with type t