Module Hardcaml.Always

Always is a DSL that lets one describe a circuit in the same style as a Verliog always block.

if and switch control constructs are provided. ($==) is used for assignment.

Code is written as lists of assignments, if and control statements.

variables;

let var = wire (zero 8) in
let var = reg r_sync enable 8 in

assignment;

var $== exp;

if statements;

if_ condition [ ... ] [ ... ]

switch statements;

switch condition [
  consti 3 0 [ ... ];
  consti 3 1 [ ... ];
  consti 3 2 [ ... ];
  consti 3 3 [ ... ];
]

signals;

let (s:signal) = q (v:guarded) in

compilation;

compile [ ... ]

example;

      let state = reg r_sync enable 2 in
      let a = wire 8 in
      compile [
        if_ a#q ==: consti 8 4 [
          a $== consti 8 2
        ] [
          switch (q state) [
          (consti 2 0) [
            a $==. 3;
            state $== const 2 1;
          ];
          (consti 2 1) [
            a $==. 2;
            state $== const 2 2;
          ];
          (consti 2 2) [
            a $==. 1;
            state $== const 2 3;
          ];
          (consti 2 3) [
            a $==. 0;
            state $== const 2 4;
          ]
        ]
      ];
      let state = state#q in
      let a = a#q in
      ....