Module Hardcaml__.Signal_graph
val sexp_of_t : t -> Ppx_sexp_conv_lib.Sexp.t
val create : Hardcaml.Signal.t Hardcaml__.Import.list -> tCreate a
Signal_graph.tfrom a list of signals (commonly, circuit outputs).
val inputs : t -> Hardcaml.Signal.t Hardcaml__.Import.list Hardcaml__.Import.Or_error.tTraverse the graph and find all inputs. Badly formed inputs (no name, or multiple names) return an error.
val outputs : ?validate:Hardcaml__.Import.bool -> t -> Hardcaml.Signal.t Hardcaml__.Import.list Hardcaml__.Import.Or_error.tReturn the outputs of the signal graph. If
validateistrue, then the outputs are checked for compatibility with circuit outputs.
val depth_first_search : ?deps:(Hardcaml.Signal.t -> Hardcaml.Signal.t Hardcaml__.Import.list) -> ?f_before:('a -> Hardcaml.Signal.t -> 'a) -> ?f_after:('a -> Hardcaml.Signal.t -> 'a) -> t -> init:'a -> 'aVisit all signals in the graph, starting at the outputs, in a depth-first manner. Each signal is visited only once.
f_beforeis called before recursing on each signal's fan-in. Similiarly,f_afteris called after recursing on the fan-in.If
depsis provided it will be used to compute signal dependencies rather than the default definition. This is useful for terminating traversals based on some condition on signals, e.g., if it's a register or a memory.
val fold : t -> init:'a -> f:('a -> Hardcaml.Signal.t -> 'a) -> 'aFold across all signals in the graph, starting at the outputs. Each signal is visited only once.
val filter : t -> f:(Hardcaml.Signal.t -> Hardcaml__.Import.bool) -> Hardcaml.Signal.t Hardcaml__.Import.listReturn a list of all signals in the graph for whom
f signalreturns true.
val iter : t -> f:(Hardcaml.Signal.t -> Hardcaml__.Import.unit) -> Hardcaml__.Import.unitIterate over all signals in the graph.
val detect_combinational_loops : t -> Hardcaml__.Import.unit Hardcaml__.Import.Or_error.tRetuns an error if the graph has a combinational loop, that is, a path from a signal back to itself that doesn't pass though a register, memory or instantiation.
val normalize_uids : t -> tnormalize_uids tcreates a copy oftthat is identical totexcept the uids are numbered starting at 1.
val fan_out_map : ?deps:(Hardcaml.Signal.t -> Hardcaml.Signal.t Hardcaml__.Import.list) -> t -> Hardcaml.Signal.Uid_set.t Hardcaml.Signal.Uid_map.tFan-out of each signal in the signal graph. The fan-out of a signal is the set of signals it drives.
val fan_in_map : ?deps:(Hardcaml.Signal.t -> Hardcaml.Signal.t Hardcaml__.Import.list) -> t -> Hardcaml.Signal.Uid_set.t Hardcaml.Signal.Uid_map.tFan-in of each signal in the signal graph. The fan-in of a signal is the set of signals that drive it.
val topological_sort : ?deps:(Hardcaml.Signal.t -> Hardcaml.Signal.t Hardcaml__.Import.list) -> t -> Hardcaml.Signal.t Hardcaml__.Import.listtopological_sort tsorts the signals intso that all the signals indeps soccur befores.
val scheduling_deps : Hardcaml.Signal.t -> Hardcaml.Signal.t Hardcaml__.Import.listSignal dependencies used for scheduling. Breaks loops through sequential elements like registers and memories.
val last_layer_of_nodes : is_input:(Hardcaml.Signal.t -> Hardcaml__.Import.bool) -> t -> Hardcaml.Signal.Uid.t Hardcaml__.Import.List.tFinal layer of combinational nodes which sit on the path between the outputs and any driving register or memory.