Module `Hardcaml__.Parameter`

module Std_logic : sig ... end: 9-state VHDL std_logic enumeration

module Std_logic_vector : sig ... end

module Bit_vector : sig ... end

module Value : sig ... end

type t = { name : Hardcaml.Parameter_name.t; value : Value.t; }

val compare : t -> t -> Hardcaml__.Import.int
val sexp_of_t : t -> Ppx_sexp_conv_lib.Sexp.t

include Hardcaml__.Import.Equal.S with type t := t

type t

val equal : t Hardcaml__.Import.Equal.equal

module Unstable : Hardcaml__.Import.Unstable with type t = t

val create : name:Hardcaml__.Import.string -> value:Value.t -> t
val find_name : t Hardcaml__.Import.list -> Hardcaml.Parameter_name.t -> Value.t Hardcaml__.Import.Option.t
val find_name_exn : t Hardcaml__.Import.list -> Hardcaml.Parameter_name.t -> Value.t
val is_subset : t Hardcaml__.Import.list -> t Hardcaml__.Import.list -> Hardcaml__.Import.bool: is_subset ts1 ts2 returns true iff every t in ts1 is in ts2.

val sort_by_name : t Hardcaml__.Import.list -> t Hardcaml__.Import.list