Parameter In_scope.1-I

include Hardcaml__.Interface_intf.Pre
include Hardcaml__.Interface_intf.Pre_partial
type 'a t
val sexp_of_t : ('a -> Ppx_sexp_conv_lib.Sexp.t) -> 'a t -> Ppx_sexp_conv_lib.Sexp.t
val iter : 'a t -> f:('a -> Hardcaml__.Import.unit) -> Hardcaml__.Import.unit
val iter2 : 'a t -> 'b t -> f:('a -> 'b -> Hardcaml__.Import.unit) -> Hardcaml__.Import.unit
val map : 'a t -> f:('a -> 'b) -> 'b t
val map2 : 'a t -> 'b t -> f:('a -> 'b -> 'c) -> 'c t
val to_list : 'a t -> 'a Hardcaml__.Import.list
val t : (Hardcaml__.Import.string * Hardcaml__.Import.int) t
include Hardcaml__.Import.Equal.S1 with type 'a t := 'a t
type 'a t
val equal : 'a Hardcaml__.Import.Equal.equal -> 'a t Hardcaml__.Import.Equal.equal
val port_names : Hardcaml__.Import.string t

RTL names specified in the interface definition - commonly also the OCaml field name.

val port_widths : Hardcaml__.Import.int t

Bit widths specified in the interface definition.

val to_alist : 'a t -> (Hardcaml__.Import.string * 'a) Hardcaml__.Import.list

Create association list indexed by field names.

val of_alist : (Hardcaml__.Import.string * 'a) Hardcaml__.Import.list -> 'a t

Create interface from association list indexed by field names

val zip : 'a t -> 'b t -> ('a * 'b) t
val zip3 : 'a t -> 'b t -> 'c t -> ('a * 'b * 'c) t
val zip4 : 'a t -> 'b t -> 'c t -> 'd t -> ('a * 'b * 'c * 'd) t
val zip5 : 'a t -> 'b t -> 'c t -> 'd t -> 'e t -> ('a * 'b * 'c * 'd * 'e) t
val map3 : 'a t -> 'b t -> 'c t -> f:('a -> 'b -> 'c -> 'd) -> 'd t
val map4 : 'a t -> 'b t -> 'c t -> 'd t -> f:('a -> 'b -> 'c -> 'd -> 'e) -> 'e t
val map5 : 'a t -> 'b t -> 'c t -> 'd t -> 'e t -> f:('a -> 'b -> 'c -> 'd -> 'e -> 'f) -> 'f t
val iter3 : 'a t -> 'b t -> 'c t -> f:('a -> 'b -> 'c -> Hardcaml__.Import.unit) -> Hardcaml__.Import.unit
val iter4 : 'a t -> 'b t -> 'c t -> 'd t -> f:('a -> 'b -> 'c -> 'd -> Hardcaml__.Import.unit) -> Hardcaml__.Import.unit
val iter5 : 'a t -> 'b t -> 'c t -> 'd t -> 'e t -> f:('a -> 'b -> 'c -> 'd -> 'e -> Hardcaml__.Import.unit) -> Hardcaml__.Import.unit
val fold : 'a t -> init:'acc -> f:('acc -> 'a -> 'acc) -> 'acc
val fold2 : 'a t -> 'b t -> init:'acc -> f:('acc -> 'a -> 'b -> 'acc) -> 'acc
val scan : 'a t -> init:'acc -> f:('acc -> 'a -> 'acc * 'b) -> 'b t
val scan2 : 'a t -> 'b t -> init:'acc -> f:('acc -> 'a -> 'b -> 'acc * 'c) -> 'c t
val offsets : ?⁠rev:Hardcaml__.Import.bool -> Hardcaml__.Import.unit -> Hardcaml__.Import.int t

Offset of each field within the interface. The first field is placed at the least significant bit, unless the rev argument is true.

val of_interface_list : 'a t Hardcaml__.Import.list -> 'a Hardcaml__.Import.list t

Take a list of interfaces and produce a single interface where each field is a list.

val to_interface_list : 'a Hardcaml__.Import.list t -> 'a t Hardcaml__.Import.list

Create a list of interfaces from a single interface where each field is a list. Raises if all lists don't have the same length.

module type Comb = Hardcaml__.Interface_intf.Comb with type 'a interface := 'a t
module Make_comb : functor (Comb : Hardcaml.Comb.S) -> Comb with type comb = Comb.t
module Of_bits : Comb with type comb = Hardcaml.Bits.t
module Of_signal : sig ... end