Module Fifo_intf.T

type 'a t = {
q : 'a;
full : 'a;
empty : 'a;
nearly_full : 'a;
nearly_empty : 'a;
used : 'a;
}
val sexp_of_t : a. ('a -> Ppx_sexp_conv_lib.Sexp.t) -> 'a t -> Ppx_sexp_conv_lib.Sexp.t
val t : (string * int) t
val iter : 'a t -> f:('a -> 'b) -> 'b
val iter2 : 'a t -> 'b t -> f:('a -> 'b -> 'c) -> 'c
val map : 'a t -> f:('a -> 'b) -> 'b t
val map2 : 'a t -> 'b t -> f:('a -> 'b -> 'c) -> 'c t
val to_list : 'a t -> 'a Hardcaml__.Ppx_deriving_hardcaml_runtime.List.t
include sig ... end
val sexp_of_t : ('a -> Ppx_sexp_conv_lib.Sexp.t) -> 'a t -> Ppx_sexp_conv_lib.Sexp.t
val iter : 'a t -> f:('a -> Hardcaml__.Import.unit) -> Hardcaml__.Import.unit
val iter2 : 'a t -> 'b t -> f:('a -> 'b -> Hardcaml__.Import.unit) -> Hardcaml__.Import.unit
val map : 'a t -> f:('a -> 'b) -> 'b t
val map2 : 'a t -> 'b t -> f:('a -> 'b -> 'c) -> 'c t
val to_list : 'a t -> 'a Hardcaml__.Import.list
val t : (Hardcaml__.Import.string * Hardcaml__.Import.int) t
val equal : 'a Hardcaml__.Import.Equal.equal -> 'a t Hardcaml__.Import.Equal.equal
val port_names : Hardcaml__.Import.string t
val port_widths : Hardcaml__.Import.int t
val to_alist : 'a t -> (Hardcaml__.Import.string * 'a) Hardcaml__.Import.list
val of_alist : (Hardcaml__.Import.string * 'a) Hardcaml__.Import.list -> 'a t
val zip : 'a t -> 'b t -> ('a * 'b) t
val zip3 : 'a t -> 'b t -> 'c t -> ('a * 'b * 'c) t
val zip4 : 'a t -> 'b t -> 'c t -> 'd t -> ('a * 'b * 'c * 'd) t
val zip5 : 'a t -> 'b t -> 'c t -> 'd t -> 'e t -> ('a * 'b * 'c * 'd * 'e) t
val map3 : 'a t -> 'b t -> 'c t -> f:('a -> 'b -> 'c -> 'd) -> 'd t
val map4 : 'a t -> 'b t -> 'c t -> 'd t -> f:('a -> 'b -> 'c -> 'd -> 'e) -> 'e t
val map5 : 'a t -> 'b t -> 'c t -> 'd t -> 'e t -> f:('a -> 'b -> 'c -> 'd -> 'e -> 'f) -> 'f t
val iter3 : 'a t -> 'b t -> 'c t -> f:('a -> 'b -> 'c -> Hardcaml__.Import.unit) -> Hardcaml__.Import.unit
val iter4 : 'a t -> 'b t -> 'c t -> 'd t -> f:('a -> 'b -> 'c -> 'd -> Hardcaml__.Import.unit) -> Hardcaml__.Import.unit
val iter5 : 'a t -> 'b t -> 'c t -> 'd t -> 'e t -> f:('a -> 'b -> 'c -> 'd -> 'e -> Hardcaml__.Import.unit) -> Hardcaml__.Import.unit
val fold : 'a t -> init:'acc -> f:('acc -> 'a -> 'acc) -> 'acc
val fold2 : 'a t -> 'b t -> init:'acc -> f:('acc -> 'a -> 'b -> 'acc) -> 'acc
val scan : 'a t -> init:'acc -> f:('acc -> 'a -> 'acc * 'b) -> 'b t
val scan2 : 'a t -> 'b t -> init:'acc -> f:('acc -> 'a -> 'b -> 'acc * 'c) -> 'c t
val offsets : ?⁠rev:Hardcaml__.Import.bool -> Hardcaml__.Import.unit -> Hardcaml__.Import.int t
val of_interface_list : 'a t Hardcaml__.Import.list -> 'a Hardcaml__.Import.list t
val to_interface_list : 'a Hardcaml__.Import.list t -> 'a t Hardcaml__.Import.list
module type Comb = sig ... end
module Make_comb : functor (Comb : Hardcaml.Comb.S) -> sig ... end
module Of_bits : sig ... end
module Of_signal : sig ... end
type 'a create_params = ?⁠nearly_empty:Hardcaml__.Import.int -> ?⁠nearly_full:Hardcaml__.Import.int -> ?⁠overflow_check:Hardcaml__.Import.bool -> ?⁠reset:Hardcaml.Signal.t -> ?⁠underflow_check:Hardcaml__.Import.bool -> ?⁠ram_attributes:Hardcaml.Rtl_attribute.t Hardcaml__.Import.list -> ?⁠scope:Hardcaml.Scope.t -> 'a
type create_fifo = (Hardcaml__.Import.unit -> capacity:Hardcaml__.Import.int -> clock:Hardcaml.Signal.t -> clear:Hardcaml.Signal.t -> wr:Hardcaml.Signal.t -> d:Hardcaml.Signal.t -> rd:Hardcaml.Signal.t -> Hardcaml.Signal.t t) create_params