Module Make.Of_signal
include Comb with type comb = Signal.t
val sexp_of_t : t -> Ppx_sexp_conv_lib.Sexp.t
val widths : t -> Hardcaml__.Import.int interfaceActual bit widths of each field.
val assert_widths : t -> Hardcaml__.Import.unitRaise if the widths of
tdo not match those specified in the interface.
val of_int : Hardcaml__.Import.int -> tEach field is set to the constant integer value provided.
val of_ints : Hardcaml__.Import.int interface -> tconsts csets each field to the integer value incusing the declared field bit width.
val const : Hardcaml__.Import.int -> tval consts : Hardcaml__.Import.int interface -> tval pack : ?rev:Hardcaml__.Import.bool -> t -> combPack interface into a vector.
val unpack : ?rev:Hardcaml__.Import.bool -> comb -> tUnpack interface from a vector.
val mux : comb -> t Hardcaml__.Import.list -> tMultiplex a list of interfaces.
val mux2 : comb -> t -> t -> tval concat : t Hardcaml__.Import.list -> tConcatenate a list of interfaces.
val priority_select : ((comb, t) With_valid.t2 Hardcaml__.Import.list -> (comb, t) With_valid.t2) Comb.optional_branching_factorval priority_select_with_default : ((comb, t) With_valid.t2 Hardcaml__.Import.list -> default:t -> t) Comb.optional_branching_factorval onehot_select : ((comb, t) With_valid.t2 Hardcaml__.Import.list -> t) Comb.optional_branching_factor
val wires : ?named:Hardcaml__.Import.bool -> ?from:t -> Hardcaml__.Import.unit -> tCreate a wire for each field. If
namedis true then wires are given the RTL field name. Iffromis provided the wire is attached to each given field infrom.
val assign : t -> t -> Hardcaml__.Import.unitval (<==) : t -> t -> Hardcaml__.Import.unitval inputs : Hardcaml__.Import.unit -> tinputs tiswires () ~named:true.
val apply_names : ?prefix:Hardcaml__.Import.string -> ?suffix:Hardcaml__.Import.string -> ?naming_op:(comb -> Hardcaml__.Import.string -> comb) -> t -> tApply name to field of the interface. Add
prefixandsuffixif specified.