Module Hardcaml__.Reg_spec

include Hardcaml.Signal.Reg_spec_
type t = Hardcaml.Signal.register
val sexp_of_t : t -> Ppx_sexp_conv_lib.Sexp.t
val create : ?⁠clear:Hardcaml.Signal.signal -> ?⁠reset:Hardcaml.Signal.signal -> Hardcaml__.Import.unit -> clock:Hardcaml.Signal.signal -> t
val override : ?⁠clock:Hardcaml.Signal.signal -> ?⁠clock_edge:Hardcaml.Edge.t -> ?⁠reset:Hardcaml.Signal.signal -> ?⁠reset_edge:Hardcaml.Edge.t -> ?⁠reset_to:Hardcaml.Signal.signal -> ?⁠clear:Hardcaml.Signal.signal -> ?⁠clear_level:Hardcaml.Level.t -> ?⁠clear_to:Hardcaml.Signal.signal -> ?⁠global_enable:Hardcaml.Signal.signal -> t -> t
val clock : t -> Hardcaml.Signal.signal
val clear : t -> Hardcaml.Signal.signal
val reset : t -> Hardcaml.Signal.signal