Module Cyclesim.With_interface

Parameters

Signature

type nonrec t = (Hardcaml.Bits.t Hardcaml__.Import.ref I.t, Hardcaml.Bits.t Hardcaml__.Import.ref O.t) t
val sexp_of_t : t -> Ppx_sexp_conv_lib.Sexp.t
val create : (?⁠port_checks:Hardcaml.Circuit.Port_checks.t -> ?⁠add_phantom_inputs:Hardcaml__.Import.bool -> Hardcaml.Circuit.With_interface(I)(O).create -> t) with_create_options Hardcaml.Circuit.with_create_options

Create a simulator using the provided Create_fn. The returned simulator ports are coerced to the input and output interface types.

val coerce : t_port_list -> t

Coerce simulator port types to use the provided input and output interfaces.