Module Hardcaml__.Bits0

type t = private {
width : Hardcaml__.Import.int;
data : Hardcaml__.Import.Bytes.t;
}
val compare : t -> t -> Hardcaml__.Import.int
val sexp_of_t : t -> Ppx_sexp_conv_lib.Sexp.t
module Comparable : Hardcaml__.Import.Comparable.S with type t := t
val bits_per_word : Hardcaml__.Import.int
val log_bits_per_word : Hardcaml__.Import.int
val shift_bits_to_bytes : Hardcaml__.Import.int
val shift_bytes_to_words : Hardcaml__.Import.int
val width_mask : Hardcaml__.Import.int
val words_of_width : Hardcaml__.Import.int -> Hardcaml__.Import.int
val empty : t
val create : Hardcaml__.Import.int -> t

create n create a n bit constant, initialized to hold all 0s.

val create_bytes : Hardcaml__.Import.int -> Hardcaml__.Import.Bytes.t

create_bytes width returns a Bytes.t large enough to hold width bits and rouneded up appropriately.

val init : width:Hardcaml__.Import.int -> data:Hardcaml__.Import.Bytes.t -> t

Construct a t with the given width and Bytes.t data.

val words : t -> Hardcaml__.Import.int

The number of 64 bit words used to represent the constant

val width : t -> Hardcaml__.Import.int

Bit width of constant