Module Rtl.Output_mode

RTL generation options.

type t =
| In_directory of Hardcaml__.Import.string

Write each circuit into a file in the given directory. The file name consists of the circuit name and the approriate file extension (.v for Verilog and .vhd for VHDL).

| To_buffer of Hardcaml__.Import.Buffer.t

Write all circuits into one buffer.

| To_channel of Hardcaml__.Import.Out_channel.t

Write all circuits to one out channel.

| To_file of Hardcaml__.Import.string

Write all circuits into one file.

val sexp_of_t : t -> Ppx_sexp_conv_lib.Sexp.t