Module Hardcaml.Recipe

Hardware generation in an imperative style.

This module is undergoing significant rewriting and refactoring, and subject to many breaking changes.

type var
type 'a t
include Hardcaml__.Import.Monad.S with type 'a t := 'a t
type 'a t
include Base__.Monad_intf.S_without_syntax with type 'a t := 'a t
type 'a t
include Base__.Monad_intf.Infix with type 'a t := 'a t
type 'a t
val (>>=) : 'a t -> ('a -> 'b t) -> 'b t

t >>= f returns a computation that sequences the computations represented by two monad elements. The resulting computation first does t to yield a value v, and then runs the computation returned by f v.

val (>>|) : 'a t -> ('a -> 'b) -> 'b t

t >>| f is t >>= (fun a -> return (f a)).

module Monad_infix : Base__.Monad_intf.Infix with type 'a t := 'a t
val bind : 'a t -> f:('a -> 'b t) -> 'b t

bind t ~f = t >>= f

val return : 'a -> 'a t

return v returns the (trivial) computation that returns v.

val map : 'a t -> f:('a -> 'b) -> 'b t

map t ~f is t >>| f.

val join : 'a t t -> 'a t

join t is t >>= (fun t' -> t').

val ignore_m : 'a t -> unit t

ignore_m t is map t ~f:(fun _ -> ()). ignore_m used to be called ignore, but we decided that was a bad name, because it shadowed the widely used Caml.ignore. Some monads still do let ignore = ignore_m for historical reasons.

val all : 'a t list -> 'a list t
val all_unit : unit t list -> unit t

Like all, but ensures that every monadic value in the list produces a unit value, all of which are discarded rather than being collected into a list.

include Base__.Monad_intf.Syntax with type 'a t := 'a t
type 'a t
module Let_syntax : sig ... end
val skip : Hardcaml__.Import.unit t

skip 1 cycle

val wait : Hardcaml__.Import.int -> Hardcaml__.Import.unit t

skip n cycles

val par : ?⁠comb_fin:Hardcaml__.Import.bool -> 'a t Hardcaml__.Import.list -> 'a Hardcaml__.Import.list t

Perform ts in parallel. comb_fin controls the finish signal generation. When false and extra cycle is taken after the ts complete to generate the fin signal. Otherwise extra combinatorial logic is generated to ensure the fin signal toggles on the same cycle as the last t to complete.

val par2 : ?⁠comb_fin:Hardcaml__.Import.bool -> 'a t -> 'b t -> ('a * 'b) t
val (|||) : 'a t -> 'b t -> ('a * 'b) t
val cond : Signal.t -> 'a t -> 'b t -> Hardcaml__.Import.unit t

cond c t f performs t if c is high, otherwise performs f

val iter : Signal.t -> 'a t -> 'a t

iter c t perform t while c is high

val forever : 'a t -> 'a t

perform t forever

val wait_while : Signal.t -> Hardcaml__.Import.unit t

wait until t is low

val wait_until : Signal.t -> Hardcaml__.Import.unit t

wait until t is high

val follow : clock:Signal.t -> enable:Signal.t -> Signal.t -> 'a t -> Signal.t * 'a

follow t and get result

val new_var : ?⁠name:Hardcaml__.Import.string -> Hardcaml__.Import.int -> var t

create an new n bit register

val read_var : var -> Signal.t t

read value of register

val assign : (var * Signal.t) Hardcaml__.Import.list -> Hardcaml__.Import.unit t

assign list of registers - takes 1 cycle

val write_var : var -> Signal.t -> Hardcaml__.Import.unit t

write register with value

val modify_var : (Signal.t -> Signal.t) -> var -> Hardcaml__.Import.unit t

modify current value of resgiter

val rewrite_var : (Signal.t -> Signal.t) -> var -> var -> Hardcaml__.Import.unit t

read a register, modify value, write a second register

module type Same = Hardcaml__.Recipe_intf.Same with type var := var with type 'a recipe := 'a t
module Same : functor (X : Interface.Pre) -> Same with type 'a same = 'a X.t
module SVar : Same with type 'a same = 'a
module SList : Same with type 'a same = 'a Hardcaml__.Import.list
module SArray : Same with type 'a same = 'a Hardcaml__.Import.array
module STuple2 : Same with type 'a same = 'a * 'a
module STuple3 : Same with type 'a same = 'a * 'a * 'a