Module Always.Variable
The type of variables in guarded assignments. Variables may be asychronous wire
s, or synchronous reg
s. The current value of the variable may be accessed through the value
field below.
val reg : Reg_spec.t -> enable:Signal.t -> width:Hardcaml__.Import.int -> t
create a register
val pipeline : depth:Hardcaml__.Import.int -> Reg_spec.t -> enable:Signal.t -> width:Hardcaml__.Import.int -> t
create a pipeline of registers