Module `Always.State_machine`

type 'a t = { current : Signal.t; is : 'a -> Signal.t; set_next : 'a -> always; switch cases does a switch on all possible states. The cases must be exhaustive and irredundant. If the cases are non-exhaustive, one can supply ~default to make them exhaustive. switch : ?⁠default:always Hardcaml__.Import.list -> 'a cases -> always; }

val sexp_of_t : ('a -> Ppx_sexp_conv_lib.Sexp.t) -> 'a t -> Ppx_sexp_conv_lib.Sexp.t

module Encoding : sig ... end

module type State = sig ... end

val create : ?⁠encoding:Encoding.t -> (module State with type t = 'a) -> Reg_spec.t -> enable:Signal.t -> 'a t: create reg_spec ~e creates a new state machine where the state is stored in a register created from reg_spec and e.