Module Hardcaml_waveterm__.Port

module Type : sig ... end
type t = {
type_ : Type.t;
port_name : Hardcaml_waveterm.Port_name.t;
width : Hardcaml_waveterm__.Import.int;
}
val compare : t -> t -> Hardcaml_waveterm__.Import.int
val sexp_of_t : t -> Ppx_sexp_conv_lib.Sexp.t