Module `Hardcaml_waveterm.Display_rules`

A Display_rules.t is an ordered list of rules that specifies the order of ports and the formatting of signals in a waveform.

A port is displayed according to the first rule that it matches, using that rule's wave format. Ports matching rules earlier in the list are displayed above ports matching rules later in the list.

module Rule : sig ... end: A Rule.t is a predicate on Port.ts that specifies the display format of matching ports.

type t

val sexp_of_t : t -> Ppx_sexp_conv_lib.Sexp.t

val empty : t
val add_above : t -> Rule.t -> t: add_above t rule returns rules where ports matching rule appear above ports matching the rules in t.

val add_below : t -> Rule.t -> t: add_below t rule returns rules where ports matching rule appear below ports matching the rules in t.

val of_list : Rule.t Hardcaml_waveterm__.Import.list -> t
val combine : above:t -> below:t -> t: combine ~above ~below returns rules where ports matching the rules in above appear above ports matching the rules in below.

val sort_ports_and_formats : t -> Port.t Hardcaml_waveterm__.Import.list -> (Port.t * Wave_format.t * Wave_format.alignment) Hardcaml_waveterm__.Import.list: Construct the port order and formatting from the display rules and ports (derived from a testbench simulation object). Unmatched ports are not shown, unless Rule.default (or a similar custom rule) is included as the last display rule.

val is_displayed : t -> Port.t -> Hardcaml_waveterm__.Import.bool: Check if a given port is displayed by any of the rules.

val is_signal_displayed : t -> Hardcaml.Signal.t -> Hardcaml_waveterm__.Import.bool: Check if a given signal (treated as an internal port) is displayed by any of the rules.