Module Recipe.SVar
val smap : f:(var -> Hardcaml.Signal.t) -> var same -> Hardcaml.Signal.t same
val szip : var same -> Hardcaml.Signal.t same -> (var * Hardcaml.Signal.t) Hardcaml__.Import.list
val newVar : Hardcaml__.Import.unit -> var same recipe
val read : var same -> Hardcaml.Signal.t same recipe
val rewrite : (Hardcaml.Signal.t same -> Hardcaml.Signal.t same) -> var same -> var same -> Hardcaml__.Import.unit recipe
val apply : (Hardcaml.Signal.t same -> Hardcaml.Signal.t same) -> var same -> Hardcaml__.Import.unit recipe
val set : var same -> Hardcaml.Signal.t same -> Hardcaml__.Import.unit recipe
val ifte : (Hardcaml.Signal.t same -> Hardcaml.Signal.t) -> var same -> 'a recipe -> 'b recipe -> Hardcaml__.Import.unit recipe
val while_ : (Hardcaml.Signal.t same -> Hardcaml.Signal.t) -> var same -> 'a recipe -> 'a recipe