Module Ram.Read_port
type t= Hardcaml.Signal.read_port={read_clock : Hardcaml.Signal.t;read_address : Hardcaml.Signal.t;read_enable : Hardcaml.Signal.t;}
val sexp_of_t : t -> Ppx_sexp_conv_lib.Sexp.t
Ram.Read_porttype t = Hardcaml.Signal.read_port = {read_clock : Hardcaml.Signal.t; |
read_address : Hardcaml.Signal.t; |
read_enable : Hardcaml.Signal.t; |
}val sexp_of_t : t -> Ppx_sexp_conv_lib.Sexp.t