Module Hardcaml.Recipe
include Hardcaml__.Recipe_intf.Recipe
module Monad : sig ... endval skip : Hardcaml__.Import.unit recipeskip 1 cycle
val wait : Hardcaml__.Import.int -> Hardcaml__.Import.unit recipeskip n cycles
val par : ?comb_fin:Hardcaml__.Import.bool -> 'a recipe Hardcaml__.Import.list -> 'a Hardcaml__.Import.list recipePerform recipes in parallel.
comb_fincontrols the finish signal generation. When false and extra cycle is taken after the recipes complete to generate thefinsignal. Otherwise extra combinatorial logic is generated to ensure thefinsignal toggles on the same cycle as the last recipe to complete.
val par2 : ?comb_fin:Hardcaml__.Import.bool -> 'a recipe -> 'b recipe -> ('a * 'b) recipeval (|||) : 'a recipe -> 'b recipe -> ('a * 'b) recipeval cond : Signal.t -> 'a recipe -> 'b recipe -> Hardcaml__.Import.unit recipecond c t fperformstifcis high, otherwise performsf
val waitWhile : Signal.t -> Hardcaml__.Import.unit recipewait until
tis low
val waitUntil : Signal.t -> Hardcaml__.Import.unit recipewait until
tis high
val newVar : ?name:Hardcaml__.Import.string -> Hardcaml__.Import.int -> var recipecreate an new
nbit register
val assign : (var * Signal.t) Hardcaml__.Import.list -> Hardcaml__.Import.unit recipeassign list of registers - takes 1 cycle
val writeVar : var -> Signal.t -> Hardcaml__.Import.unit recipewrite register with value
val modifyVar : (Signal.t -> Signal.t) -> var -> Hardcaml__.Import.unit recipemodify current value of resgiter
val rewriteVar : (Signal.t -> Signal.t) -> var -> var -> Hardcaml__.Import.unit reciperead a register, modify value, write a second register
module type Same = Hardcaml__.Recipe_intf.Same with type var := var with type 'a recipe := 'a recipemodule SList : Same with type 'a same = 'a Hardcaml__.Import.listmodule SArray : Same with type 'a same = 'a Hardcaml__.Import.array