Module Hardcaml.Recipe
include Hardcaml__.Recipe_intf.Recipe
module Monad : sig ... end
val skip : Hardcaml__.Import.unit recipe
skip 1 cycle
val wait : Hardcaml__.Import.int -> Hardcaml__.Import.unit recipe
skip n cycles
val par : ?comb_fin:Hardcaml__.Import.bool -> 'a recipe Hardcaml__.Import.list -> 'a Hardcaml__.Import.list recipe
Perform recipes in parallel.
comb_fin
controls the finish signal generation. When false and extra cycle is taken after the recipes complete to generate thefin
signal. Otherwise extra combinatorial logic is generated to ensure thefin
signal toggles on the same cycle as the last recipe to complete.
val par2 : ?comb_fin:Hardcaml__.Import.bool -> 'a recipe -> 'b recipe -> ('a * 'b) recipe
val (|||) : 'a recipe -> 'b recipe -> ('a * 'b) recipe
val cond : Signal.t -> 'a recipe -> 'b recipe -> Hardcaml__.Import.unit recipe
cond c t f
performst
ifc
is high, otherwise performsf
val waitWhile : Signal.t -> Hardcaml__.Import.unit recipe
wait until
t
is low
val waitUntil : Signal.t -> Hardcaml__.Import.unit recipe
wait until
t
is high
val newVar : ?name:Hardcaml__.Import.string -> Hardcaml__.Import.int -> var recipe
create an new
n
bit register
val assign : (var * Signal.t) Hardcaml__.Import.list -> Hardcaml__.Import.unit recipe
assign list of registers - takes 1 cycle
val writeVar : var -> Signal.t -> Hardcaml__.Import.unit recipe
write register with value
val modifyVar : (Signal.t -> Signal.t) -> var -> Hardcaml__.Import.unit recipe
modify current value of resgiter
val rewriteVar : (Signal.t -> Signal.t) -> var -> var -> Hardcaml__.Import.unit recipe
read a register, modify value, write a second register
module type Same = Hardcaml__.Recipe_intf.Same with type var := var with type 'a recipe := 'a recipe
module SList : Same with type 'a same = 'a Hardcaml__.Import.list
module SArray : Same with type 'a same = 'a Hardcaml__.Import.array