Module Parameter.Std_logic

9-state VHDL std_logic enumeration

type t =
| U

Uninitialized

| X

Unknown

| L0

Logic 0

| L1

Logic 1

| Z

High impedance

| W

Weak - neither prefer 0 or 1

| L

Weak - prefer 0

| H

Weak - prefer 1

| Don't_care

Dont care

val compare : t -> t -> Hardcaml__.Import.int
val all : t Hardcaml__.Import.list
val sexp_of_t : t -> Ppx_sexp_conv_lib.Sexp.t
val u : t
val x : t
val l0 : t
val l1 : t
val z : t
val w : t
val l : t
val h : t
val don't_care : t
module Variants : sig ... end
include Hardcaml__.Import.Equal.S with type t := t
type t
val equal : t Hardcaml__.Import.Equal.equal
module Unstable : Hardcaml__.Import.Unstable with type t = t
val to_int : t -> Hardcaml__.Import.int

Provide the index of t in textual order. When passing a std_logic parameter from verilog to vhdl, we need to encode this type into an integer. For example, L1 = 4'd3.

val of_char_exn : Hardcaml__.Import.char -> t

The OCaml char used in of_char and to_char is the same as used in VHDL.

val to_char : t -> Hardcaml__.Import.char