Module `Empty.Of_signal`

include Comb with type comb = Signal.t

type 'a interface
type comb = Signal.t
type t = comb interface

val sexp_of_t : t -> Ppx_sexp_conv_lib.Sexp.t

val widths : t -> Hardcaml__.Import.int interface: Actual bit widths of each field.

val assert_widths : t -> Hardcaml__.Import.unit: Raise if the widths of t do not match those specified in the interface.

val const : Hardcaml__.Import.int -> t: Each field is set to the constant integer value provided.

val consts : Hardcaml__.Import.int interface -> t: consts c sets each field to the integer value in c using the declared field bit width.

val pack : ?⁠rev:Hardcaml__.Import.bool -> t -> comb: Pack interface into a vector.

val unpack : ?⁠rev:Hardcaml__.Import.bool -> comb -> t: Unpack interface from a vector.

val mux : comb -> t Hardcaml__.Import.list -> t: Multiplex a list of interfaces.

val mux2 : comb -> t -> t -> t
val concat : t Hardcaml__.Import.list -> t: Concatenate a list of interfaces.

val wires : ?⁠named:Hardcaml__.Import.bool -> ?⁠from:t -> Hardcaml__.Import.unit -> t: Create a wire for each field. If named is true then wires are given the RTL field name. If from is provided the wire is attached to each given field in from.

val assign : t -> t -> Hardcaml__.Import.unit
val (<==) : t -> t -> Hardcaml__.Import.unit
val inputs : Hardcaml__.Import.unit -> t: inputs t is wires () ~named:true.

val outputs : t -> t: outputs t is wires () ~from:t ~named:true.

val apply_names : ?⁠prefix:Hardcaml__.Import.string -> ?⁠suffix:Hardcaml__.Import.string -> ?⁠naming_op:(comb -> Hardcaml__.Import.string -> comb) -> t -> t: Apply name to field of the interface. Add prefix and suffix if specified.