Module Hardcaml.Bits
include Hardcaml__.Bits_intf.Bits
val compare : t -> t -> Hardcaml__.Import.int
val sexp_of_t : t -> Ppx_sexp_conv_lib.Sexp.t
include Comb.S with type t := t
val sexp_of_t : t -> Ppx_sexp_conv_lib.Sexp.t
val empty : t
the empty signal
val is_empty : t -> Hardcaml__.Import.bool
val (--) : t -> Hardcaml__.Import.string -> t
names a signal
let a = a -- "a" in ...
signals may have multiple names.
val width : t -> Hardcaml__.Import.int
returns the width (number of bits) of a signal.
let w = width s in ...
val address_bits_for : Hardcaml__.Import.int -> Hardcaml__.Import.int
addess_bits_for num_elements
returns the address width required to indexnum_elements
.It is the same as
Int.ceil_log2
, except it wll return a minimum value of 1 (since you cannot have 0 width vectors). Raises ifnum_elements
is< 0
.
val num_bits_to_represent : Hardcaml__.Import.int -> Hardcaml__.Import.int
num_bits_to_represent x
returns the number of bits required to represent the numberx
, which should be>= 0
.
val of_constant : Constant.t -> t
val to_constant : t -> Constant.t
val constb : Hardcaml__.Import.string -> t
convert binary string to constant
val consti : width:Hardcaml__.Import.int -> Hardcaml__.Import.int -> t
convert integer to constant
val consti32 : width:Hardcaml__.Import.int -> Hardcaml__.Import.int32 -> t
val consti64 : width:Hardcaml__.Import.int -> Hardcaml__.Import.int64 -> t
val consthu : width:Hardcaml__.Import.int -> Hardcaml__.Import.string -> t
convert unsigned hex string to constant
val consths : width:Hardcaml__.Import.int -> Hardcaml__.Import.string -> t
convert signed hex string to constant
val constd : width:Hardcaml__.Import.int -> Hardcaml__.Import.string -> t
convert decimal string to constant
val constv : Hardcaml__.Import.string -> t
convert verilog style string to constant
val constibl : Hardcaml__.Import.int Hardcaml__.Import.list -> t
convert IntbitsList to constant
val const : Hardcaml__.Import.string -> t
convert verilog style or binary string to constant
val concat_msb : t Hardcaml__.Import.list -> t
concat ts
concatenates a list of signals - the msb of the head of the list will become the msb of the result.let c = concat [ a; b; c ] in ...
concat
raises ifts
is empty or if anyt
ints
is empty.
val concat_lsb : t Hardcaml__.Import.list -> t
Similar to
concat_msb
except the lsb of the head of the list will become the lsb of the result.
val concat_msb_e : t Hardcaml__.Import.list -> t
same as
concat_msb
except empty signals are first filtered out
val concat_lsb_e : t Hardcaml__.Import.list -> t
same as
concat_lsb
except empty signals are first filtered out
val vdd : t
logic 1
val is_vdd : t -> Hardcaml__.Import.bool
val gnd : t
logic 0
val is_gnd : t -> Hardcaml__.Import.bool
val zero : Hardcaml__.Import.int -> t
zero w
makes a the zero valued constant of widthw
val ones : Hardcaml__.Import.int -> t
ones w
makes a constant of all ones of widthw
val one : Hardcaml__.Import.int -> t
one w
makes a one valued constant of widthw
val select : t -> Hardcaml__.Import.int -> Hardcaml__.Import.int -> t
select t hi lo
selects fromt
bits in the rangehi
...lo
, inclusive.select
raises unlesshi
andlo
fall within0 .. width t - 1
andhi >= lo
.
val select_e : t -> Hardcaml__.Import.int -> Hardcaml__.Import.int -> t
same as
select
except invalid indices returnempty
val bit : t -> Hardcaml__.Import.int -> t
select a single bit
val drop_bottom : t -> Hardcaml__.Import.int -> t
drop_bottom s n
drop bottomn
bits ofs
val drop_top : t -> Hardcaml__.Import.int -> t
drop_top s n
drop topn
bits ofs
val sel_bottom : t -> Hardcaml__.Import.int -> t
sel_bottom s n
select bottomn
bits ofs
val sel_top : t -> Hardcaml__.Import.int -> t
sel_top s n
select topn
bits ofs
val (.:[]) : t -> (Hardcaml__.Import.int * Hardcaml__.Import.int) -> t
x.:[hi, lo]
==select x hi lo
val (.:+[]) : t -> (Hardcaml__.Import.int * Hardcaml__.Import.int Hardcaml__.Import.option) -> t
x.:+[lo, width]
==select x (lo + width - 1) lo
. Ifwidth
isNone
it selects all remaining msbs of the vector iex.:+[lo,None]
==drop_bottom x lo
val (.:-[]) : t -> (Hardcaml__.Import.int Hardcaml__.Import.option * Hardcaml__.Import.int) -> t
x.:-[hi, width]
==select x hi (hi - width + 1)
. Ifhi
isNone
it defaults to the msb of the vector iex.:-[None, width]
==sel_top x width
val (.:()) : t -> Hardcaml__.Import.int -> t
x.(i)
==bit x i
val insert : into:t -> t -> at_offset:Hardcaml__.Import.int -> t
insert ~into:t x ~at_offset
insertx
intot
at given offet
val sel : t -> (Hardcaml__.Import.int * Hardcaml__.Import.int) -> t
val mux : t -> t Hardcaml__.Import.list -> t
multiplexer.
let m = mux sel inputs in ...
Given
l
=List.length inputs
andw
=width sel
the following conditions must hold.l
<= 2**w
,l
>= 2If
l
< 2**w
, the last input is repeated.All inputs provided must have the same width, which will in turn be equal to the width of
m
.
val mux2 : t -> t -> t -> t
mux2 c t f
2 input multiplexer. Selectst
ifc
is high otherwisef
.t
andf
must have same width andc
must be 1 bit.Equivalent to
mux c [f; t]
val mux_init : t -> Hardcaml__.Import.int -> f:(Hardcaml__.Import.int -> t) -> t
val cases : t -> t -> (Hardcaml__.Import.int * t) Hardcaml__.Import.list -> t
case mux
val matches : ?resize:(t -> Hardcaml__.Import.int -> t) -> ?default:t -> t -> (Hardcaml__.Import.int * t) Hardcaml__.Import.list -> t
match mux
val (^:.) : t -> Hardcaml__.Import.int -> t
val (~:) : t -> t
logical not
val (-:.) : t -> Hardcaml__.Import.int -> t
val negate : t -> t
negation
val (>=+.) : t -> Hardcaml__.Import.int -> t
val to_string : t -> Hardcaml__.Import.string
create string from signal
val to_int : t -> Hardcaml__.Import.int
to_int t
treatst
as unsigned and resizes it to fit exactly within an OCamlInt.t
.- If
width t > Int.num_bits
then the upper bits are truncated. - If
width t >= Int.num_bits
andbit t (Int.num_bits-1) = vdd
(i.e. the msb of the resultingInt.t
is set), then the result is negative. - If
t
isSignal.t
and not a constant value, an exception is raised.
- If
val to_sint : t -> Hardcaml__.Import.int
to_sint t
treatst
as signed and resizes it to fit exactly within an OCamlInt.t
.- If
width t > Int.num_bits
then the upper bits are truncated. - If
t
isSignal.t
and not a constant value, an exception is raised.
- If
val to_int32 : t -> Hardcaml__.Import.int32
val to_sint32 : t -> Hardcaml__.Import.int32
val to_int64 : t -> Hardcaml__.Import.int64
val to_sint64 : t -> Hardcaml__.Import.int64
val to_bstr : t -> Hardcaml__.Import.string
create binary string from signal
val bits_msb : t -> t Hardcaml__.Import.list
convert signal to a list of bits with msb at head of list
val bits_lsb : t -> t Hardcaml__.Import.list
convert signal to a list of bits with lsb at head of list
val to_array : t -> t Hardcaml__.Import.array
to_array s
convert signals
to array of bits with lsb at index 0
val of_array : t Hardcaml__.Import.array -> t
of_array a
convert arraya
of bits to signal with lsb at index 0
val repeat : t -> Hardcaml__.Import.int -> t
repeat signal n times
val split_in_half_msb : t -> t * t
split signal in half. The most significant bits will be in the left half of the returned tuple.
val split_lsb : ?exact:Hardcaml__.Import.bool -> part_width:Hardcaml__.Import.int -> t -> t Hardcaml__.Import.list
Split signal into a list of signals with width equal to
part_width
. The least significant bits are at the head of the returned list. Ifexact
istrue
the input signal width must be exactly divisable bypart_width
. Whenexact
isfalse
and the input signal width is not exactly divisible bypart_width
, the last element will contains residual bits.eg:
split_lsb ~part_width:4 16b0001_0010_0011_0100 = [ 4b0100; 4b0011; 4b0010; 4b0001 ] split_lsb ~exact:false ~part_width:4 17b11_0001_0010_0011_0100 = [ 4b0100; 4b0011; 4b0010; 4b0001; 2b11 ]
val split_msb : ?exact:Hardcaml__.Import.bool -> part_width:Hardcaml__.Import.int -> t -> t Hardcaml__.Import.list
Like
split_lsb
except the most significant bits are at the head of the returned list. Residual bits whenexact
isfalse
goes to the last element of the list, so in the general casesplit_lsb
is not necessarily equivalent tosplit_msb |> List.rev
.
val sll : t -> Hardcaml__.Import.int -> t
shift left logical
val srl : t -> Hardcaml__.Import.int -> t
shift right logical
val sra : t -> Hardcaml__.Import.int -> t
shift right arithmetic
val rotl : t -> Hardcaml__.Import.int -> t
rotate left
val rotr : t -> Hardcaml__.Import.int -> t
rotate right
val uresize : t -> Hardcaml__.Import.int -> t
uresize t w
returns the unsigned resize oft
to widthw
. Ifw = width t
, this is a no-op. Ifw < width t
, thisselect
s thew
low bits oft
. Ifw > width t
, this extendst
withzero (width t - w)
.
val sresize : t -> Hardcaml__.Import.int -> t
sresize t w
returns the signed resize oft
to widthw
. Ifw = width t
, this is a no-op. Ifw < width t
, thisselect
s thew
low bits oft
. Ifw > width t
, this extendst
withwidth t - w
copies ofmsb t
.
val resize_list : resize:(t -> Hardcaml__.Import.int -> t) -> t Hardcaml__.Import.list -> t Hardcaml__.Import.list
resize_list ?resize l
finds the maximum width inl
and appliesresize el max
to each element.
val resize_op2 : resize:(t -> Hardcaml__.Import.int -> t) -> (t -> t -> t) -> t -> t -> t
resize_op2 ~resize f a b
appliesresize x w
toa
andb
wherew
is the maximum of their widths. It then returnsf a b
val reduce : f:('a -> 'a -> 'a) -> 'a Hardcaml__.Import.list -> 'a
fold 'op' though list
val mod_counter : max:Hardcaml__.Import.int -> t -> t
mod_counter max t
isif t = max then 0 else (t + 1)
, and can be used to count from 0 to (max-1) then from zero again. If max == 1<<n, then a comparator is not generated and overflow arithmetic used instead. If
val tree : arity:Hardcaml__.Import.int -> f:('a Hardcaml__.Import.list -> 'a) -> 'a Hardcaml__.Import.list -> 'a
tree ~arity ~f input
creates a tree of operations. The arity of the operator is configurable.tree
raises ifinput = []
.
val priority_select : (t With_valid.t Hardcaml__.Import.list -> t With_valid.t) Hardcaml__.Comb_intf.optional_branching_factor
priority_select cases
returns the value associated with the first case whosevalid
signal is high.valid
will be set low in the returnedWith_valid.t
if no case is selected.
val priority_select_with_default : (t With_valid.t Hardcaml__.Import.list -> default:t -> t) Hardcaml__.Comb_intf.optional_branching_factor
Same as
priority_select
except returnsdefault
if no case matches.
val onehot_select : (t With_valid.t Hardcaml__.Import.list -> t) Hardcaml__.Comb_intf.optional_branching_factor
Select a case where one and only one
valid
signal is enabled. If more than one case isvalid
then the return value is undefined. If no cases are valid,0
is returned by the current implementation, though this should not be relied upon.
val popcount : (t -> t) Hardcaml__.Comb_intf.optional_branching_factor
popcount t
returns the number of bits set int
.
val is_pow2 : (t -> t) Hardcaml__.Comb_intf.optional_branching_factor
is_pow2 t
returns a bit to indicate ift
is a power of 2.
val leading_ones : (t -> t) Hardcaml__.Comb_intf.optional_branching_factor
leading_ones t
returns the number of consecutive1
s from the most significant bit oft
down.
val trailing_ones : (t -> t) Hardcaml__.Comb_intf.optional_branching_factor
trailing_ones t
returns the number of consecutive1
s from the least significant bit oft
up.
val leading_zeros : (t -> t) Hardcaml__.Comb_intf.optional_branching_factor
leading_zeros t
returns the number of consecutive0
s from the most significant bit oft
down.
val trailing_zeros : (t -> t) Hardcaml__.Comb_intf.optional_branching_factor
trailing_zeros t
returns the number of consecutive0
s from the least significant bit oft
up.
val floor_log2 : (t -> t With_valid.t) Hardcaml__.Comb_intf.optional_branching_factor
floor_log2 x
returns the floor of log-base-2 ofx
.x
is treated as unsigned and an error is indicated byvalid = gnd
in the return value ifx = 0
.
val ceil_log2 : (t -> t With_valid.t) Hardcaml__.Comb_intf.optional_branching_factor
ceil_log2 x
returns the ceiling of log-base-2 ofx
.x
is treated as unsigned and an error is indicated byvalid = gnd
in the return value ifx = 0
.
val random : width:Hardcaml__.Import.int -> t
create random constant vector of given width
module type TypedMath = Hardcaml__.Comb_intf.TypedMath with type t := t
include Hardcaml__.Import.Comparator.S with type t := t
val comparator : (t, comparator_witness) Hardcaml__.Import.Comparator.comparator
module Unsafe : sig ... end
module Mutable : sig ... end with type bits := t
Mutable
is a mutable bits used byCyclesim
for efficiency.
val pp : Hardcaml__.Import.Formatter.t -> t -> Hardcaml__.Import.unit
Pretty printer.