Module `Hardcaml_waveterm.Display_rules`

module Rule : sig ... end: A Rule.t is a predicate on Port.ts that specifies the display format of matching ports.

type t

val sexp_of_t : t -> Ppx_sexp_conv_lib.Sexp.t

val empty : t
val add_above : t -> Rule.t -> t: add_above t rule returns rules where ports matching rule appear above ports matching the rules in t.

val add_below : t -> Rule.t -> t: add_below t rule returns rules where ports matching rule appear below ports matching the rules in t.

val of_list : Rule.t Import.list -> t
val combine : above:t -> below:t -> t: combine ~above ~below returns rules where ports matching the rules in above appear above ports matching the rules in below.

val sort_ports_and_formats : t -> Port.t Import.list -> (Port.t * Wave_format.t) Import.list: Construct the port order and formatting from the display rules and ports (derived from a testbench simulation object). Unmatched ports are not shown, unless Rule.default (or a similar custom rule) is included as the last display rule.