Module Xilinx.XMake

Parameters

• X : S
• L : LutSize

Signature

val x_lut : LutEqn.t -> Hardcaml.Signal.t -> Hardcaml.Signal.t

val x_map : LutEqn.t -> Hardcaml.Signal.t Hardcaml__.Import.list -> Hardcaml.Signal.t

val x_and : Hardcaml.Signal.t -> Hardcaml.Signal.t -> Hardcaml.Signal.t

val x_or : Hardcaml.Signal.t -> Hardcaml.Signal.t -> Hardcaml.Signal.t

val x_xor : Hardcaml.Signal.t -> Hardcaml.Signal.t -> Hardcaml.Signal.t

val x_not : Hardcaml.Signal.t -> Hardcaml.Signal.t

val x_reduce_carry : Hardcaml__.Import.bool -> (LutEqn.t -> LutEqn.t -> LutEqn.t) -> Hardcaml.Signal.t -> Hardcaml.Signal.t -> Hardcaml.Signal.t -> Hardcaml.Signal.t

val x_and_reduce : Hardcaml.Signal.t -> Hardcaml.Signal.t

val x_or_reduce : Hardcaml.Signal.t -> Hardcaml.Signal.t

val x_reduce_tree : (LutEqn.t -> LutEqn.t -> LutEqn.t) -> Hardcaml.Signal.t -> Hardcaml.Signal.t

val x_add_carry : LutEqn.t -> Hardcaml.Signal.t -> Hardcaml.Signal.t -> Hardcaml.Signal.t -> Hardcaml.Signal.t * Hardcaml.Signal.t

val x_add : Hardcaml.Signal.t -> Hardcaml.Signal.t -> Hardcaml.Signal.t

val x_sub : Hardcaml.Signal.t -> Hardcaml.Signal.t -> Hardcaml.Signal.t

val x_mux_add_carry : LutEqn.t -> Hardcaml.Signal.t -> Hardcaml.Signal.t -> (Hardcaml.Signal.t * Hardcaml.Signal.t) -> Hardcaml.Signal.t -> Hardcaml.Signal.t * Hardcaml.Signal.t

val x_mux_add : Hardcaml.Signal.t -> (Hardcaml.Signal.t * Hardcaml.Signal.t) -> Hardcaml.Signal.t -> Hardcaml.Signal.t

x_mux_add x (a, a') b gives (x ? a : a') + b

val x_mux_sub : Hardcaml.Signal.t -> Hardcaml.Signal.t -> (Hardcaml.Signal.t * Hardcaml.Signal.t) -> Hardcaml.Signal.t

x_mux_sub x a (b, b') gives a - (x ? b : b')

val x_eq : Hardcaml.Signal.t -> Hardcaml.Signal.t -> Hardcaml.Signal.t

val x_lt : Hardcaml.Signal.t -> Hardcaml.Signal.t -> Hardcaml.Signal.t

val x_mux : Hardcaml.Signal.t -> Hardcaml.Signal.t Hardcaml__.Import.list -> Hardcaml.Signal.t

val x_mulu : Hardcaml.Signal.t -> Hardcaml.Signal.t -> Hardcaml.Signal.t

val x_muls : Hardcaml.Signal.t -> Hardcaml.Signal.t -> Hardcaml.Signal.t