module V1: sig .. end
include ??
val compare : Host_and_port.t -> Host_and_port.t -> int
val bin_t : Host_and_port.t Bin_prot.Type_class.t
val bin_read_t : Host_and_port.t Bin_prot.Read.reader
val __bin_read_t__ : (int -> Host_and_port.t) Bin_prot.Read.reader
val bin_reader_t : Host_and_port.t Bin_prot.Type_class.reader
val bin_size_t : Host_and_port.t Bin_prot.Size.sizer
val bin_write_t : Host_and_port.t Bin_prot.Write.writer
val bin_writer_t : Host_and_port.t Bin_prot.Type_class.writer
val t_of_sexp : Sexplib.Sexp.t -> Host_and_port.t
val sexp_of_t : Host_and_port.t -> Sexplib.Sexp.t