opam-version: "2.0"
maintainer: "Jane Street developers"
authors: ["Jane Street Group, LLC"]
homepage: "https://github.com/janestreet/hardcaml_of_verilog"
bug-reports: "https://github.com/janestreet/hardcaml_of_verilog/issues"
dev-repo: "git+https://github.com/janestreet/hardcaml_of_verilog.git"
doc: "https://ocaml.janestreet.com/ocaml-core/latest/doc/hardcaml_of_verilog/index.html"
license: "MIT"
build: [
  ["dune" "build" "-p" name "-j" jobs]
]
depends: [
  "ocaml"           {>= "4.14.0"}
  "base"            {= "v0.17~preview.129.11+135"}
  "core"            {= "v0.17~preview.129.11+135"}
  "core_unix"       {= "v0.17~preview.129.11+135"}
  "hardcaml"        {= "v0.17~preview.129.11+135"}
  "hardcaml_verify" {= "v0.17~preview.129.11+135"}
  "jsonaf"          {= "v0.17~preview.129.11+135"}
  "ppx_hardcaml"    {= "v0.17~preview.129.11+135"}
  "ppx_jane"        {= "v0.17~preview.129.11+135"}
  "ppx_jsonaf_conv" {= "v0.17~preview.129.11+135"}
  "stdio"           {= "v0.17~preview.129.11+135"}
  "dune"            {>= "2.0.0"}
]
available: arch != "arm32" & arch != "x86_32"
synopsis: "Convert Verilog to a Hardcaml design"
description: "
The opensource synthesis tool yosys is used to convert a verilog design to a JSON based
netlist representation. This library can load the JSON netlist and build a hardcaml
circuit.

Code can also be generated to wrap the conversion process using Hardcaml interfaces.
"
url {
src: "https://github.com/janestreet/hardcaml_of_verilog/archive/c891b6b34ddba97f9af9c1399533e11d68a3e40a.tar.gz"
checksum: "sha256=32e6e8da388edbed9b5a14f2b4191a0205a05c37f0e97d22da07fed4e1fc3bb9"
}

flags: deprecated
post-messages: [
  "IMPORTANT: The bleeding edge repository mirror on ocaml.janestreet.com is being deprecated in favor of our official GitHub repository."
  "To ensure you receive the latest packages and updates, please update your repository URL by running:"
  "  opam repo set-url janestreet-bleeding https://github.com/janestreet/opam-repository.git"
]