Parameter `XSynthesize.1-X`

val lut : Hardcaml__.Import.int64 -> Signal.t -> Signal.t
val muxcy : Signal.t -> Signal.t -> Signal.t -> Signal.t
val inv : Signal.t -> Signal.t
val xorcy : Signal.t -> Signal.t -> Signal.t
val muxf5 : Signal.t -> Signal.t -> Signal.t -> Signal.t
val muxf6 : Signal.t -> Signal.t -> Signal.t -> Signal.t
val muxf7 : Signal.t -> Signal.t -> Signal.t -> Signal.t
val muxf8 : Signal.t -> Signal.t -> Signal.t -> Signal.t
val fdce : Signal.t -> Signal.t -> Signal.t -> Signal.t -> Signal.t
val fdpe : Signal.t -> Signal.t -> Signal.t -> Signal.t -> Signal.t
val mult_and : Signal.t -> Signal.t -> Signal.t
val ram1s : Signal.t -> Signal.t -> Signal.t -> Signal.t -> Signal.t