Module `Xilinx.Hardcaml_api`

Hardcaml simulation based models of Xilinx primitives

val lut : Hardcaml__.Import.int64 -> Hardcaml.Signal.t -> Hardcaml.Signal.t
val muxcy : Hardcaml.Signal.t -> Hardcaml.Signal.t -> Hardcaml.Signal.t -> Hardcaml.Signal.t
val inv : Hardcaml.Signal.t -> Hardcaml.Signal.t
val xorcy : Hardcaml.Signal.t -> Hardcaml.Signal.t -> Hardcaml.Signal.t
val muxf5 : Hardcaml.Signal.t -> Hardcaml.Signal.t -> Hardcaml.Signal.t -> Hardcaml.Signal.t
val muxf6 : Hardcaml.Signal.t -> Hardcaml.Signal.t -> Hardcaml.Signal.t -> Hardcaml.Signal.t
val muxf7 : Hardcaml.Signal.t -> Hardcaml.Signal.t -> Hardcaml.Signal.t -> Hardcaml.Signal.t
val muxf8 : Hardcaml.Signal.t -> Hardcaml.Signal.t -> Hardcaml.Signal.t -> Hardcaml.Signal.t
val fdce : Hardcaml.Signal.t -> Hardcaml.Signal.t -> Hardcaml.Signal.t -> Hardcaml.Signal.t -> Hardcaml.Signal.t
val fdpe : Hardcaml.Signal.t -> Hardcaml.Signal.t -> Hardcaml.Signal.t -> Hardcaml.Signal.t -> Hardcaml.Signal.t
val mult_and : Hardcaml.Signal.t -> Hardcaml.Signal.t -> Hardcaml.Signal.t
val ram1s : Hardcaml.Signal.t -> Hardcaml.Signal.t -> Hardcaml.Signal.t -> Hardcaml.Signal.t -> Hardcaml.Signal.t