Module Value.Variants
val bit : (Hardcaml__.Import.bool -> t) Variantslib.Variant.tval bit_vector : (Bit_vector.t -> t) Variantslib.Variant.tval bool : (Hardcaml__.Import.bool -> t) Variantslib.Variant.tval int : (Hardcaml__.Import.int -> t) Variantslib.Variant.tval real : (Hardcaml__.Import.float -> t) Variantslib.Variant.tval std_logic : (Std_logic.t -> t) Variantslib.Variant.tval std_logic_vector : (Std_logic_vector.t -> t) Variantslib.Variant.tval std_ulogic : (Std_logic.t -> t) Variantslib.Variant.tval std_ulogic_vector : (Std_logic_vector.t -> t) Variantslib.Variant.tval string : (Hardcaml__.Import.string -> t) Variantslib.Variant.tval fold : init:'acc__ -> bit:('acc__ -> (Hardcaml__.Import.bool -> t) Variantslib.Variant.t -> 'acc__) -> bit_vector:('acc__ -> (Bit_vector.t -> t) Variantslib.Variant.t -> 'acc__) -> bool:('acc__ -> (Hardcaml__.Import.bool -> t) Variantslib.Variant.t -> 'acc__) -> int:('acc__ -> (Hardcaml__.Import.int -> t) Variantslib.Variant.t -> 'acc__) -> real:('acc__ -> (Hardcaml__.Import.float -> t) Variantslib.Variant.t -> 'acc__) -> std_logic:('acc__ -> (Std_logic.t -> t) Variantslib.Variant.t -> 'acc__) -> std_logic_vector:('acc__ -> (Std_logic_vector.t -> t) Variantslib.Variant.t -> 'acc__) -> std_ulogic:('acc__ -> (Std_logic.t -> t) Variantslib.Variant.t -> 'acc__) -> std_ulogic_vector:('acc__ -> (Std_logic_vector.t -> t) Variantslib.Variant.t -> 'acc__) -> string:('acc__ -> (Hardcaml__.Import.string -> t) Variantslib.Variant.t -> 'acc__) -> 'acc__val iter : bit:((Hardcaml__.Import.bool -> t) Variantslib.Variant.t -> Hardcaml__.Import.unit) -> bit_vector:((Bit_vector.t -> t) Variantslib.Variant.t -> Hardcaml__.Import.unit) -> bool:((Hardcaml__.Import.bool -> t) Variantslib.Variant.t -> Hardcaml__.Import.unit) -> int:((Hardcaml__.Import.int -> t) Variantslib.Variant.t -> Hardcaml__.Import.unit) -> real:((Hardcaml__.Import.float -> t) Variantslib.Variant.t -> Hardcaml__.Import.unit) -> std_logic:((Std_logic.t -> t) Variantslib.Variant.t -> Hardcaml__.Import.unit) -> std_logic_vector:((Std_logic_vector.t -> t) Variantslib.Variant.t -> Hardcaml__.Import.unit) -> std_ulogic:((Std_logic.t -> t) Variantslib.Variant.t -> Hardcaml__.Import.unit) -> std_ulogic_vector:((Std_logic_vector.t -> t) Variantslib.Variant.t -> Hardcaml__.Import.unit) -> string:((Hardcaml__.Import.string -> t) Variantslib.Variant.t -> Hardcaml__.Import.unit) -> Hardcaml__.Import.unitval map : t -> bit:((Hardcaml__.Import.bool -> t) Variantslib.Variant.t -> Hardcaml__.Import.bool -> 'result__) -> bit_vector:((Bit_vector.t -> t) Variantslib.Variant.t -> Bit_vector.t -> 'result__) -> bool:((Hardcaml__.Import.bool -> t) Variantslib.Variant.t -> Hardcaml__.Import.bool -> 'result__) -> int:((Hardcaml__.Import.int -> t) Variantslib.Variant.t -> Hardcaml__.Import.int -> 'result__) -> real:((Hardcaml__.Import.float -> t) Variantslib.Variant.t -> Hardcaml__.Import.float -> 'result__) -> std_logic:((Std_logic.t -> t) Variantslib.Variant.t -> Std_logic.t -> 'result__) -> std_logic_vector:((Std_logic_vector.t -> t) Variantslib.Variant.t -> Std_logic_vector.t -> 'result__) -> std_ulogic:((Std_logic.t -> t) Variantslib.Variant.t -> Std_logic.t -> 'result__) -> std_ulogic_vector:((Std_logic_vector.t -> t) Variantslib.Variant.t -> Std_logic_vector.t -> 'result__) -> string:((Hardcaml__.Import.string -> t) Variantslib.Variant.t -> Hardcaml__.Import.string -> 'result__) -> 'result__val make_matcher : bit:((Hardcaml__.Import.bool -> t) Variantslib.Variant.t -> 'acc__0 -> (Hardcaml__.Import.bool -> 'result__) * 'acc__1) -> bit_vector:((Bit_vector.t -> t) Variantslib.Variant.t -> 'acc__1 -> (Bit_vector.t -> 'result__) * 'acc__2) -> bool:((Hardcaml__.Import.bool -> t) Variantslib.Variant.t -> 'acc__2 -> (Hardcaml__.Import.bool -> 'result__) * 'acc__3) -> int:((Hardcaml__.Import.int -> t) Variantslib.Variant.t -> 'acc__3 -> (Hardcaml__.Import.int -> 'result__) * 'acc__4) -> real:((Hardcaml__.Import.float -> t) Variantslib.Variant.t -> 'acc__4 -> (Hardcaml__.Import.float -> 'result__) * 'acc__5) -> std_logic:((Std_logic.t -> t) Variantslib.Variant.t -> 'acc__5 -> (Std_logic.t -> 'result__) * 'acc__6) -> std_logic_vector:((Std_logic_vector.t -> t) Variantslib.Variant.t -> 'acc__6 -> (Std_logic_vector.t -> 'result__) * 'acc__7) -> std_ulogic:((Std_logic.t -> t) Variantslib.Variant.t -> 'acc__7 -> (Std_logic.t -> 'result__) * 'acc__8) -> std_ulogic_vector:((Std_logic_vector.t -> t) Variantslib.Variant.t -> 'acc__8 -> (Std_logic_vector.t -> 'result__) * 'acc__9) -> string:((Hardcaml__.Import.string -> t) Variantslib.Variant.t -> 'acc__9 -> (Hardcaml__.Import.string -> 'result__) * 'acc__10) -> 'acc__0 -> (t -> 'result__) * 'acc__10val to_rank : t -> Hardcaml__.Import.intval to_name : t -> Hardcaml__.Import.stringval descriptions : (Hardcaml__.Import.string * Hardcaml__.Import.int) Hardcaml__.Import.list