Module `Hardcaml.Graph`

Write circuit as graph.

val write_dot_rank : Hardcaml__.Import.Out_channel.t -> Circuit.t -> Hardcaml__.Import.unit
val write_gdl : ?⁠names:Hardcaml__.Import.bool -> ?⁠widths:Hardcaml__.Import.bool -> ?⁠consts:Hardcaml__.Import.bool -> ?⁠clocks:Hardcaml__.Import.bool -> Hardcaml__.Import.Out_channel.t -> Circuit.t -> Hardcaml__.Import.unit: write a GDL (graph description language) file of the given circuit

val aisee3 : ?⁠args:Hardcaml__.Import.string -> ?⁠names:Hardcaml__.Import.bool -> ?⁠widths:Hardcaml__.Import.bool -> ?⁠consts:Hardcaml__.Import.bool -> ?⁠clocks:Hardcaml__.Import.bool -> Circuit.t -> Hardcaml__.Import.unit: launch aisee3 to visualize the given circuit