Module `Hardcaml.Design_rule_checks`

Simple circuit analsysis passes for common issues.

val verify_clock_pins : expected_clock_pins:Hardcaml__.Import.string Hardcaml__.Import.list -> Circuit.t -> Hardcaml__.Import.unit: Raises if there exists a seqential element (register or memory) whose clock input pin is not in expected_clock_pins. Clocks are defined by the name of input clock signals into the circuit.