Module Xilinx.XMake

Parameters

Signature

module LutEqn : sig ... end
val x_lut : LutEqn.t -> Signal.t -> Signal.t
val x_map : LutEqn.t -> Signal.t Hardcaml__.Import.list -> Signal.t
val x_and : Signal.t -> Signal.t -> Signal.t
val x_or : Signal.t -> Signal.t -> Signal.t
val x_xor : Signal.t -> Signal.t -> Signal.t
val x_not : Signal.t -> Signal.t
val x_reduce_carry : Hardcaml__.Import.bool -> (LutEqn.t -> LutEqn.t -> LutEqn.t) -> Signal.t -> Signal.t -> Signal.t -> Signal.t
val x_and_reduce : Signal.t -> Signal.t
val x_or_reduce : Signal.t -> Signal.t
val x_reduce_tree : (LutEqn.t -> LutEqn.t -> LutEqn.t) -> Signal.t -> Signal.t
val x_add_carry : LutEqn.t -> Signal.t -> Signal.t -> Signal.t -> Signal.t * Signal.t
val x_add : Signal.t -> Signal.t -> Signal.t
val x_sub : Signal.t -> Signal.t -> Signal.t
val x_mux_add_carry : LutEqn.t -> Signal.t -> Signal.t -> (Signal.t * Signal.t) -> Signal.t -> Signal.t * Signal.t
val x_mux_add : Signal.t -> (Signal.t * Signal.t) -> Signal.t -> Signal.t

x_mux_add x (a, a') b gives (x ? a : a') + b

val x_mux_sub : Signal.t -> Signal.t -> (Signal.t * Signal.t) -> Signal.t

x_mux_sub x a (b, b') gives a - (x ? b : b')

val x_eq : Signal.t -> Signal.t -> Signal.t
val x_lt : Signal.t -> Signal.t -> Signal.t
val x_mux : Signal.t -> Signal.t Hardcaml__.Import.list -> Signal.t
val x_mulu : Signal.t -> Signal.t -> Signal.t
val x_muls : Signal.t -> Signal.t -> Signal.t