val
make_creator : mem_total:((
t,
bigint)
Fieldslib.Field.t -> 'acc__0 -> ('input__ ->
bigint)
* 'acc__1) -> mem_free:((
t,
bigint)
Fieldslib.Field.t -> 'acc__1 -> ('input__ ->
bigint)
* 'acc__2) -> buffers:((
t,
bigint)
Fieldslib.Field.t -> 'acc__2 -> ('input__ ->
bigint)
* 'acc__3) -> cached:((
t,
bigint)
Fieldslib.Field.t -> 'acc__3 -> ('input__ ->
bigint)
* 'acc__4) -> swap_cached:((
t,
bigint)
Fieldslib.Field.t -> 'acc__4 -> ('input__ ->
bigint)
* 'acc__5) -> active:((
t,
bigint)
Fieldslib.Field.t -> 'acc__5 -> ('input__ ->
bigint)
* 'acc__6) -> inactive:((
t,
bigint)
Fieldslib.Field.t -> 'acc__6 -> ('input__ ->
bigint)
* 'acc__7) -> swap_total:((
t,
bigint)
Fieldslib.Field.t -> 'acc__7 -> ('input__ ->
bigint)
* 'acc__8) -> swap_free:((
t,
bigint)
Fieldslib.Field.t -> 'acc__8 -> ('input__ ->
bigint)
* 'acc__9) -> dirty:((
t,
bigint)
Fieldslib.Field.t -> 'acc__9 -> ('input__ ->
bigint)
* 'acc__10) -> writeback:((
t,
bigint)
Fieldslib.Field.t -> 'acc__10 -> ('input__ ->
bigint)
* 'acc__11) -> anon_pages:((
t,
bigint)
Fieldslib.Field.t -> 'acc__11 -> ('input__ ->
bigint)
* 'acc__12) -> mapped:((
t,
bigint)
Fieldslib.Field.t -> 'acc__12 -> ('input__ ->
bigint)
* 'acc__13) -> slab:((
t,
bigint)
Fieldslib.Field.t -> 'acc__13 -> ('input__ ->
bigint)
* 'acc__14) -> page_tables:((
t,
bigint)
Fieldslib.Field.t -> 'acc__14 -> ('input__ ->
bigint)
* 'acc__15) -> nfs_unstable:((
t,
bigint)
Fieldslib.Field.t -> 'acc__15 -> ('input__ ->
bigint)
* 'acc__16) -> bounce:((
t,
bigint)
Fieldslib.Field.t -> 'acc__16 -> ('input__ ->
bigint)
* 'acc__17) -> commit_limit:((
t,
bigint)
Fieldslib.Field.t -> 'acc__17 -> ('input__ ->
bigint)
* 'acc__18) -> committed_as:((
t,
bigint)
Fieldslib.Field.t -> 'acc__18 -> ('input__ ->
bigint)
* 'acc__19) -> vmalloc_total:((
t,
bigint)
Fieldslib.Field.t -> 'acc__19 -> ('input__ ->
bigint)
* 'acc__20) -> vmalloc_used:((
t,
bigint)
Fieldslib.Field.t -> 'acc__20 -> ('input__ ->
bigint)
* 'acc__21) -> vmalloc_chunk:((
t,
bigint)
Fieldslib.Field.t -> 'acc__21 -> ('input__ ->
bigint)
* 'acc__22) -> 'acc__0 -> ('input__ ->
t)
* 'acc__22