Up
Module
Fields_of_cpu_t
Signature
val
names : string list
val
guest : (
cpu_t
,
bigint
option)
Fieldslib.Field.t
val
steal : (
cpu_t
,
bigint
option)
Fieldslib.Field.t
val
softirq : (
cpu_t
,
bigint
option)
Fieldslib.Field.t
val
irq : (
cpu_t
,
bigint
option)
Fieldslib.Field.t
val
iowait : (
cpu_t
,
bigint
option)
Fieldslib.Field.t
val
idle : (
cpu_t
,
bigint
)
Fieldslib.Field.t
val
sys : (
cpu_t
,
bigint
)
Fieldslib.Field.t
val
nice : (
cpu_t
,
bigint
)
Fieldslib.Field.t
val
user : (
cpu_t
,
bigint
)
Fieldslib.Field.t
val
fold : init:'acc__0 -> user:('acc__0 -> (
cpu_t
,
bigint
)
Fieldslib.Field.t
-> 'acc__1) -> nice:('acc__1 -> (
cpu_t
,
bigint
)
Fieldslib.Field.t
-> 'acc__2) -> sys:('acc__2 -> (
cpu_t
,
bigint
)
Fieldslib.Field.t
-> 'acc__3) -> idle:('acc__3 -> (
cpu_t
,
bigint
)
Fieldslib.Field.t
-> 'acc__4) -> iowait:('acc__4 -> (
cpu_t
,
bigint
option)
Fieldslib.Field.t
-> 'acc__5) -> irq:('acc__5 -> (
cpu_t
,
bigint
option)
Fieldslib.Field.t
-> 'acc__6) -> softirq:('acc__6 -> (
cpu_t
,
bigint
option)
Fieldslib.Field.t
-> 'acc__7) -> steal:('acc__7 -> (
cpu_t
,
bigint
option)
Fieldslib.Field.t
-> 'acc__8) -> guest:('acc__8 -> (
cpu_t
,
bigint
option)
Fieldslib.Field.t
-> 'acc__9) -> 'acc__9
val
make_creator : user:((
cpu_t
,
bigint
)
Fieldslib.Field.t
-> 'acc__0 -> ('input__ ->
bigint
) * 'acc__1) -> nice:((
cpu_t
,
bigint
)
Fieldslib.Field.t
-> 'acc__1 -> ('input__ ->
bigint
) * 'acc__2) -> sys:((
cpu_t
,
bigint
)
Fieldslib.Field.t
-> 'acc__2 -> ('input__ ->
bigint
) * 'acc__3) -> idle:((
cpu_t
,
bigint
)
Fieldslib.Field.t
-> 'acc__3 -> ('input__ ->
bigint
) * 'acc__4) -> iowait:((
cpu_t
,
bigint
option)
Fieldslib.Field.t
-> 'acc__4 -> ('input__ ->
bigint
option) * 'acc__5) -> irq:((
cpu_t
,
bigint
option)
Fieldslib.Field.t
-> 'acc__5 -> ('input__ ->
bigint
option) * 'acc__6) -> softirq:((
cpu_t
,
bigint
option)
Fieldslib.Field.t
-> 'acc__6 -> ('input__ ->
bigint
option) * 'acc__7) -> steal:((
cpu_t
,
bigint
option)
Fieldslib.Field.t
-> 'acc__7 -> ('input__ ->
bigint
option) * 'acc__8) -> guest:((
cpu_t
,
bigint
option)
Fieldslib.Field.t
-> 'acc__8 -> ('input__ ->
bigint
option) * 'acc__9) -> 'acc__0 -> ('input__ ->
cpu_t
) * 'acc__9
val
create : user:
bigint
-> nice:
bigint
-> sys:
bigint
-> idle:
bigint
-> iowait:
bigint
option -> irq:
bigint
option -> softirq:
bigint
option -> steal:
bigint
option -> guest:
bigint
option ->
cpu_t
val
map : user:((
cpu_t
,
bigint
)
Fieldslib.Field.t
->
bigint
) -> nice:((
cpu_t
,
bigint
)
Fieldslib.Field.t
->
bigint
) -> sys:((
cpu_t
,
bigint
)
Fieldslib.Field.t
->
bigint
) -> idle:((
cpu_t
,
bigint
)
Fieldslib.Field.t
->
bigint
) -> iowait:((
cpu_t
,
bigint
option)
Fieldslib.Field.t
->
bigint
option) -> irq:((
cpu_t
,
bigint
option)
Fieldslib.Field.t
->
bigint
option) -> softirq:((
cpu_t
,
bigint
option)
Fieldslib.Field.t
->
bigint
option) -> steal:((
cpu_t
,
bigint
option)
Fieldslib.Field.t
->
bigint
option) -> guest:((
cpu_t
,
bigint
option)
Fieldslib.Field.t
->
bigint
option) ->
cpu_t
val
iter : user:((
cpu_t
,
bigint
)
Fieldslib.Field.t
-> unit) -> nice:((
cpu_t
,
bigint
)
Fieldslib.Field.t
-> unit) -> sys:((
cpu_t
,
bigint
)
Fieldslib.Field.t
-> unit) -> idle:((
cpu_t
,
bigint
)
Fieldslib.Field.t
-> unit) -> iowait:((
cpu_t
,
bigint
option)
Fieldslib.Field.t
-> unit) -> irq:((
cpu_t
,
bigint
option)
Fieldslib.Field.t
-> unit) -> softirq:((
cpu_t
,
bigint
option)
Fieldslib.Field.t
-> unit) -> steal:((
cpu_t
,
bigint
option)
Fieldslib.Field.t
-> unit) -> guest:((
cpu_t
,
bigint
option)
Fieldslib.Field.t
-> unit) -> unit
val
for_all : user:((
cpu_t
,
bigint
)
Fieldslib.Field.t
-> bool) -> nice:((
cpu_t
,
bigint
)
Fieldslib.Field.t
-> bool) -> sys:((
cpu_t
,
bigint
)
Fieldslib.Field.t
-> bool) -> idle:((
cpu_t
,
bigint
)
Fieldslib.Field.t
-> bool) -> iowait:((
cpu_t
,
bigint
option)
Fieldslib.Field.t
-> bool) -> irq:((
cpu_t
,
bigint
option)
Fieldslib.Field.t
-> bool) -> softirq:((
cpu_t
,
bigint
option)
Fieldslib.Field.t
-> bool) -> steal:((
cpu_t
,
bigint
option)
Fieldslib.Field.t
-> bool) -> guest:((
cpu_t
,
bigint
option)
Fieldslib.Field.t
-> bool) -> bool
val
exists : user:((
cpu_t
,
bigint
)
Fieldslib.Field.t
-> bool) -> nice:((
cpu_t
,
bigint
)
Fieldslib.Field.t
-> bool) -> sys:((
cpu_t
,
bigint
)
Fieldslib.Field.t
-> bool) -> idle:((
cpu_t
,
bigint
)
Fieldslib.Field.t
-> bool) -> iowait:((
cpu_t
,
bigint
option)
Fieldslib.Field.t
-> bool) -> irq:((
cpu_t
,
bigint
option)
Fieldslib.Field.t
-> bool) -> softirq:((
cpu_t
,
bigint
option)
Fieldslib.Field.t
-> bool) -> steal:((
cpu_t
,
bigint
option)
Fieldslib.Field.t
-> bool) -> guest:((
cpu_t
,
bigint
option)
Fieldslib.Field.t
-> bool) -> bool
val
to_list : user:((
cpu_t
,
bigint
)
Fieldslib.Field.t
-> 'elem__) -> nice:((
cpu_t
,
bigint
)
Fieldslib.Field.t
-> 'elem__) -> sys:((
cpu_t
,
bigint
)
Fieldslib.Field.t
-> 'elem__) -> idle:((
cpu_t
,
bigint
)
Fieldslib.Field.t
-> 'elem__) -> iowait:((
cpu_t
,
bigint
option)
Fieldslib.Field.t
-> 'elem__) -> irq:((
cpu_t
,
bigint
option)
Fieldslib.Field.t
-> 'elem__) -> softirq:((
cpu_t
,
bigint
option)
Fieldslib.Field.t
-> 'elem__) -> steal:((
cpu_t
,
bigint
option)
Fieldslib.Field.t
-> 'elem__) -> guest:((
cpu_t
,
bigint
option)
Fieldslib.Field.t
-> 'elem__) -> 'elem__ list
val
map_poly : ([<
| `Read
| `Set_and_create
],
cpu_t
, 'x0)
Fieldslib.Field.user
-> 'x0 list
module
Direct
: sig .. end