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Module Fields

Signature

val names : string list
val nivcsw : (t, int64) Fieldslib.Field.t
val nvcsw : (t, int64) Fieldslib.Field.t
val nsignals : (t, int64) Fieldslib.Field.t
val msgrcv : (t, int64) Fieldslib.Field.t
val msgsnd : (t, int64) Fieldslib.Field.t
val oublock : (t, int64) Fieldslib.Field.t
val inblock : (t, int64) Fieldslib.Field.t
val nswap : (t, int64) Fieldslib.Field.t
val majflt : (t, int64) Fieldslib.Field.t
val minflt : (t, int64) Fieldslib.Field.t
val isrss : (t, int64) Fieldslib.Field.t
val idrss : (t, int64) Fieldslib.Field.t
val ixrss : (t, int64) Fieldslib.Field.t
val maxrss : (t, int64) Fieldslib.Field.t
val stime : (t, float) Fieldslib.Field.t
val utime : (t, float) Fieldslib.Field.t
val fold : init:'acc__0 -> utime:('acc__0 -> (t, float) Fieldslib.Field.t -> 'acc__1) -> stime:('acc__1 -> (t, float) Fieldslib.Field.t -> 'acc__2) -> maxrss:('acc__2 -> (t, int64) Fieldslib.Field.t -> 'acc__3) -> ixrss:('acc__3 -> (t, int64) Fieldslib.Field.t -> 'acc__4) -> idrss:('acc__4 -> (t, int64) Fieldslib.Field.t -> 'acc__5) -> isrss:('acc__5 -> (t, int64) Fieldslib.Field.t -> 'acc__6) -> minflt:('acc__6 -> (t, int64) Fieldslib.Field.t -> 'acc__7) -> majflt:('acc__7 -> (t, int64) Fieldslib.Field.t -> 'acc__8) -> nswap:('acc__8 -> (t, int64) Fieldslib.Field.t -> 'acc__9) -> inblock:('acc__9 -> (t, int64) Fieldslib.Field.t -> 'acc__10) -> oublock:('acc__10 -> (t, int64) Fieldslib.Field.t -> 'acc__11) -> msgsnd:('acc__11 -> (t, int64) Fieldslib.Field.t -> 'acc__12) -> msgrcv:('acc__12 -> (t, int64) Fieldslib.Field.t -> 'acc__13) -> nsignals:('acc__13 -> (t, int64) Fieldslib.Field.t -> 'acc__14) -> nvcsw:('acc__14 -> (t, int64) Fieldslib.Field.t -> 'acc__15) -> nivcsw:('acc__15 -> (t, int64) Fieldslib.Field.t -> 'acc__16) -> 'acc__16
val make_creator : utime:((t, float) Fieldslib.Field.t -> 'acc__0 -> ('input__ -> float) * 'acc__1) -> stime:((t, float) Fieldslib.Field.t -> 'acc__1 -> ('input__ -> float) * 'acc__2) -> maxrss:((t, int64) Fieldslib.Field.t -> 'acc__2 -> ('input__ -> int64) * 'acc__3) -> ixrss:((t, int64) Fieldslib.Field.t -> 'acc__3 -> ('input__ -> int64) * 'acc__4) -> idrss:((t, int64) Fieldslib.Field.t -> 'acc__4 -> ('input__ -> int64) * 'acc__5) -> isrss:((t, int64) Fieldslib.Field.t -> 'acc__5 -> ('input__ -> int64) * 'acc__6) -> minflt:((t, int64) Fieldslib.Field.t -> 'acc__6 -> ('input__ -> int64) * 'acc__7) -> majflt:((t, int64) Fieldslib.Field.t -> 'acc__7 -> ('input__ -> int64) * 'acc__8) -> nswap:((t, int64) Fieldslib.Field.t -> 'acc__8 -> ('input__ -> int64) * 'acc__9) -> inblock:((t, int64) Fieldslib.Field.t -> 'acc__9 -> ('input__ -> int64) * 'acc__10) -> oublock:((t, int64) Fieldslib.Field.t -> 'acc__10 -> ('input__ -> int64) * 'acc__11) -> msgsnd:((t, int64) Fieldslib.Field.t -> 'acc__11 -> ('input__ -> int64) * 'acc__12) -> msgrcv:((t, int64) Fieldslib.Field.t -> 'acc__12 -> ('input__ -> int64) * 'acc__13) -> nsignals:((t, int64) Fieldslib.Field.t -> 'acc__13 -> ('input__ -> int64) * 'acc__14) -> nvcsw:((t, int64) Fieldslib.Field.t -> 'acc__14 -> ('input__ -> int64) * 'acc__15) -> nivcsw:((t, int64) Fieldslib.Field.t -> 'acc__15 -> ('input__ -> int64) * 'acc__16) -> 'acc__0 -> ('input__ -> t) * 'acc__16
val create : utime:float -> stime:float -> maxrss:int64 -> ixrss:int64 -> idrss:int64 -> isrss:int64 -> minflt:int64 -> majflt:int64 -> nswap:int64 -> inblock:int64 -> oublock:int64 -> msgsnd:int64 -> msgrcv:int64 -> nsignals:int64 -> nvcsw:int64 -> nivcsw:int64 -> t
val map : utime:((t, float) Fieldslib.Field.t -> float) -> stime:((t, float) Fieldslib.Field.t -> float) -> maxrss:((t, int64) Fieldslib.Field.t -> int64) -> ixrss:((t, int64) Fieldslib.Field.t -> int64) -> idrss:((t, int64) Fieldslib.Field.t -> int64) -> isrss:((t, int64) Fieldslib.Field.t -> int64) -> minflt:((t, int64) Fieldslib.Field.t -> int64) -> majflt:((t, int64) Fieldslib.Field.t -> int64) -> nswap:((t, int64) Fieldslib.Field.t -> int64) -> inblock:((t, int64) Fieldslib.Field.t -> int64) -> oublock:((t, int64) Fieldslib.Field.t -> int64) -> msgsnd:((t, int64) Fieldslib.Field.t -> int64) -> msgrcv:((t, int64) Fieldslib.Field.t -> int64) -> nsignals:((t, int64) Fieldslib.Field.t -> int64) -> nvcsw:((t, int64) Fieldslib.Field.t -> int64) -> nivcsw:((t, int64) Fieldslib.Field.t -> int64) -> t
val iter : utime:((t, float) Fieldslib.Field.t -> unit) -> stime:((t, float) Fieldslib.Field.t -> unit) -> maxrss:((t, int64) Fieldslib.Field.t -> unit) -> ixrss:((t, int64) Fieldslib.Field.t -> unit) -> idrss:((t, int64) Fieldslib.Field.t -> unit) -> isrss:((t, int64) Fieldslib.Field.t -> unit) -> minflt:((t, int64) Fieldslib.Field.t -> unit) -> majflt:((t, int64) Fieldslib.Field.t -> unit) -> nswap:((t, int64) Fieldslib.Field.t -> unit) -> inblock:((t, int64) Fieldslib.Field.t -> unit) -> oublock:((t, int64) Fieldslib.Field.t -> unit) -> msgsnd:((t, int64) Fieldslib.Field.t -> unit) -> msgrcv:((t, int64) Fieldslib.Field.t -> unit) -> nsignals:((t, int64) Fieldslib.Field.t -> unit) -> nvcsw:((t, int64) Fieldslib.Field.t -> unit) -> nivcsw:((t, int64) Fieldslib.Field.t -> unit) -> unit
val for_all : utime:((t, float) Fieldslib.Field.t -> bool) -> stime:((t, float) Fieldslib.Field.t -> bool) -> maxrss:((t, int64) Fieldslib.Field.t -> bool) -> ixrss:((t, int64) Fieldslib.Field.t -> bool) -> idrss:((t, int64) Fieldslib.Field.t -> bool) -> isrss:((t, int64) Fieldslib.Field.t -> bool) -> minflt:((t, int64) Fieldslib.Field.t -> bool) -> majflt:((t, int64) Fieldslib.Field.t -> bool) -> nswap:((t, int64) Fieldslib.Field.t -> bool) -> inblock:((t, int64) Fieldslib.Field.t -> bool) -> oublock:((t, int64) Fieldslib.Field.t -> bool) -> msgsnd:((t, int64) Fieldslib.Field.t -> bool) -> msgrcv:((t, int64) Fieldslib.Field.t -> bool) -> nsignals:((t, int64) Fieldslib.Field.t -> bool) -> nvcsw:((t, int64) Fieldslib.Field.t -> bool) -> nivcsw:((t, int64) Fieldslib.Field.t -> bool) -> bool
val exists : utime:((t, float) Fieldslib.Field.t -> bool) -> stime:((t, float) Fieldslib.Field.t -> bool) -> maxrss:((t, int64) Fieldslib.Field.t -> bool) -> ixrss:((t, int64) Fieldslib.Field.t -> bool) -> idrss:((t, int64) Fieldslib.Field.t -> bool) -> isrss:((t, int64) Fieldslib.Field.t -> bool) -> minflt:((t, int64) Fieldslib.Field.t -> bool) -> majflt:((t, int64) Fieldslib.Field.t -> bool) -> nswap:((t, int64) Fieldslib.Field.t -> bool) -> inblock:((t, int64) Fieldslib.Field.t -> bool) -> oublock:((t, int64) Fieldslib.Field.t -> bool) -> msgsnd:((t, int64) Fieldslib.Field.t -> bool) -> msgrcv:((t, int64) Fieldslib.Field.t -> bool) -> nsignals:((t, int64) Fieldslib.Field.t -> bool) -> nvcsw:((t, int64) Fieldslib.Field.t -> bool) -> nivcsw:((t, int64) Fieldslib.Field.t -> bool) -> bool
val to_list : utime:((t, float) Fieldslib.Field.t -> 'elem__) -> stime:((t, float) Fieldslib.Field.t -> 'elem__) -> maxrss:((t, int64) Fieldslib.Field.t -> 'elem__) -> ixrss:((t, int64) Fieldslib.Field.t -> 'elem__) -> idrss:((t, int64) Fieldslib.Field.t -> 'elem__) -> isrss:((t, int64) Fieldslib.Field.t -> 'elem__) -> minflt:((t, int64) Fieldslib.Field.t -> 'elem__) -> majflt:((t, int64) Fieldslib.Field.t -> 'elem__) -> nswap:((t, int64) Fieldslib.Field.t -> 'elem__) -> inblock:((t, int64) Fieldslib.Field.t -> 'elem__) -> oublock:((t, int64) Fieldslib.Field.t -> 'elem__) -> msgsnd:((t, int64) Fieldslib.Field.t -> 'elem__) -> msgrcv:((t, int64) Fieldslib.Field.t -> 'elem__) -> nsignals:((t, int64) Fieldslib.Field.t -> 'elem__) -> nvcsw:((t, int64) Fieldslib.Field.t -> 'elem__) -> nivcsw:((t, int64) Fieldslib.Field.t -> 'elem__) -> 'elem__ list
val map_poly : ([<
| `Read
| `Set_and_create
], t, 'x0) Fieldslib.Field.user -> 'x0 list
module Direct : sig .. end